SU1427568A1 - Voltage digitizer - Google Patents

Abstract

The invention relates to computing and can be used to convert voltage into code in digital paths of control and monitoring systems. The invention allows to expand the functional possibilities. This is achieved by the fact that a converter containing a voltage divider, a switchboard, a comparing unit, a code-to-voltage converter, a pulse distributor, a register, a clock generator, AND elements, OR elements, triggers, an encoder, delay elements, comparison blocks, triggers are entered , reversible shift register, three OR elements, AND elements, delay element, analog switches, analog switch, voltage multiplier, voltage module block, and OR group of elements. 1 hp f-ly, 1 ill. §

Description

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The invention relates to computing and can be used to transform voltage code in the construction of digital receiving paths of control and control systems.

The aim of the invention is to expand the scope.

The drawing shows the functional diagram of the Converter.

The converter contains an input bus 1 analog switch 2, a voltage module block 3, which includes an inverting amplifier 4 and diodes 5, 6 an analog switch, an analog switch 8, a voltage multiplier 9 with two times multiplier steps, divider 10 voltage pair with division stages that differ by half, a group of elements OR 11 containing diodes 12 and 13, a switch; 1A, comparing unit 15, a converter 16 code to voltage, RS - trigger 17, comparing unit 18, RS -trigger 19, element OR.20, element 21 delay, RS-trigger 22, element And 23, pulse distributor 24, register 25, bus 26 of the mantissa sign, bus 27 of the mantissa code, 28 clock generator, performed on RS-trigger 29 and generator 30 of pulses, delay element 31, OR element 32, delay element 33, element OR 34, RS flip-flop 35, AND 36 element, comparing block 37, delay element 38, AND 39 element, AND 40 element, OR 41 element, reversing shift register 42, RS-flip-flop 43, bus 44, order sign, encoder 45, the bus of the 46 code order and the bus 47 launch.

The converter works as follows.

Input voltage 1 is applied to the input bus. The trigger pulse, which is fed through bus 47, sets RS flip-flops 19 and 22 to one state, valve 24, register 25 and RS flip-flop 43 to the zero state, in the reverse shift register 42 zero bit, in the first the output group is set to one, and the rest to zero, which corresponds to the zero order of the number code. The high potential from the direct output of the RS flip-flop 22 opens element 23. And the pulse 31 delayed by element 31 for the duration of transient processes in the indicated nodes

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c 35 40

45 50 55

the start-up translates the RS-flip-flop 29 of the generator 28 into one state. A high potential from the direct output of this llS flip-flop starts generator 30, and opens analog key 2. The voltage to be converted from analog key 2 goes to block 3 and to the matching block 18. If the voltage to be converted is positive, then the matching block 18 and the pulse From this block, it arrives at the K input of the RS flip-flop 19, sets it to the zero state (positive sign of the mantissa), and if the voltage to be converted is negative, then the pulse at the output of the compare block 18 is absent and the RS flip-flop 19 remains in unity m state (negative sign of the mantissa).

The pulse of the generator 30 through the element And 23 enters the counting input of the distributor 24. From the first output of the distributor 24, the pulse sets the unit 25 to the high register de-register and, delayed by element 21, returns the RS flip-flop 22 to the zero state, stopping the passage of subsequent pulses of the generator 30 through the element And 23 to the distributor 24.

In accordance with the mantissa code, the converter 16 generates a voltage supplied to the comparison blocks 15 and 37. At the same time, the converted voltage from the output of the block 3 arrives at the input of the comparison block 37. If the converted voltage is less than the voltage of the converter 16, then Comparison block 37, an impulse appears that sets the RS flip-flop 43 to one (negative order of the number). A high potential from the direct output of the RS flip-flop 43 will open the element E39 and will commute from the information shift circuit in the reverse shift register 42 towards the higher bits.

If the voltage to be converted is greater than the voltage of the converter 16, then there is no pulse at the output of the comparison block 37, the RS flip-flop 43 remains in the zero state (positive order). The element 40 will open and the information shift circuits in the reverse shift register 42 will be switched in the direction of the lower bits. In addition, a high potential is 1427568

A direct drive from the inverse of you-switch 14 and the first input of the RS-flip-flop 43, the input of the converting unit 15, receives a voltage from the analog terminal twice as much as in the prech 7 via an analog switch of the last clock. If this voltage 8 is connected to the multiplier 9 or is also less than the voltage supplied

to the door 10. Delayed element 38 on the second input of the comparison unit

the impulse from the first output is distributed-15, then it is similar to that described due to

tel 24 through the elements of And 39 and 40, respectively, about the pulse from the generator 30

responsibly zeroing the zero bit d.jg (p1-1) th register bit 42 has zeroed the reversing shift register 42c, and (t-2) -th setting in unit sets the unit to the first or other state. Thus, with the start of this register, the correspondence works up to the time when

correspondingly (depending on the state of which the voltage coming from the pull of the RS flip-flop 43). By this time the switch 14 to the first input

delayed by the element 33 of the pulse of the comparative block 15 will not

element 31, the RS flip-flops 17 and 35 of the voltage is greater than or equal to the voltage, are set to one state. The input to the second input of the comparison

High potential from the direct output of 15 from the output of the converter

RS flip-flop 35 opens element 16. When a comparing

And 36, AC output of the RS-flip-flop 17 -block 15 its output impulse is set to an analog key 7. The input transforms the RS-flip-flop 35 into zero

the voltage across the divider 10 or the state, closing the passage of the multiplier 9 depending on the positive pulses of the generator 30 on the shift of the RS flip-flop 43 and the analog 25 Shch input of the register 42.

the switch 8 goes to comm-register A2 remains in this state 14. In accordance with the code of the p d-tion, until the next pulse is detected, determined by the state of the reverse start-up. The state of the register 42 of the shearing shift register 42 corresponds to the unitary code of the order

The corresponding input of the switch is the voltage to be converted. This code

the converted voltage is converted by the encoder 45 into the first position of the input comparing the block binary code and fed to

15. tire 46. The order is removed from

Suppose that the KS flip-flop 43 on the direct output RS of the flip-flop 43 on the shodil is in the zero position. Togdan 4. The same impulse of comparing

the analog switch 8 connects the block 15 through element 20 OR the reference voltage to the divider 10. puts the RS flip-flop 22 into the state

In the reverse shift register unit. Prk this impulses with

42, the original unit will be installed on the generator 30;

In the higher order, and the next AND 23 to the counting input is distribution, in switch 14 there will be a switch 24 and the formation of

whose key, which connects the stu-code of the voltage mantissa, is received-: the stub of the divider 10, which corresponds to the search through the switch 14 to the first

greater weakening of the source voltage of the comparing unit 15.

convertible voltage nickname. The re-first of these pulses sets the following trigger register 25 to the first input of the matching register.

unit 15, the voltage comes from the one-to-one state (the first was in

great weakening. If it is for example a single state), connect to

The voltage is less than the voltage supplied to the second input of the comparison unit 15 to the second input of the comparison unit 15; the additional voltage equal to the flow of the latter does not work. Since half of the tension of the first (senior)

And 36 is open with a high potential discharge of the converter 16. If the total from the direct output of the RS flip-flop is 35, these voltages are higher than the voltage,

then the impulse from the generator 30 through the element 14 coming from the output of the switch

ment And 36 is fed to the shifter cd the first input of the comparison block

input of register 42 and sets one-55 second register trigger 25

On the next, (t -1) th, bit, is set to the initial zero

wrapped the md bit of this register. state, if not, it remains

In this case, the following key is included. On the trail of lean tact about; -

izvodi7 with balancing the impact of the next trigger, etc. (as usual bit balancing) The binary register code 25 enters the Q bus 27, and the sign value of the mantissa is removed from the direct output of the iRS flip-flop 19 to the bus 26. j If, when selecting the value of i, the unit will be in unit state trigger low-order zero register register 42, then the pulse; the output of this trigger is set to the zero state RS-trigger 35 and to the single state RS-trigger 22. The receipt of pulses from the generator 30 to the shift input; register 42 through element 36 and is pre-; edge; Register 42 is set to zero order. The switch 114 connects to the first input of the crushing unit 15 an input convertible voltage, mine divider MO. In addition, the clock pulses from the generator 30 begin to flow through the element AND 23 to the input of the distributor 24. The determination of the mantissa code corresponding to the input voltage begins, similarly to that described. The last impulse of the distribution 24 sets the RS-trigger .29 to the outcome) 1st (zero) state. The generator 30 stops forming and impulses. After the conversion is complete, the device is in this state until the next trigger pulse arrives.

If in the preparatory stage the RS-flip-flop 43 turned out to be in the single position, then the initial unit is installed in the first trigger of the register 42, the information shift circuit in the register 42 commutes towards the higher bits and the first voltage is connected to the switch 14 through a multiplier with steps multiplied by multiples of two. Initially, the switch 14 connects to the comparison unit 15 a voltage with a minimum force () at the first input. If this voltage is less than the voltage supplied to the second input of the comparison unit 15, then the latter does not work. Since element 36 is open, the next impulse from generator 30 through element 36 is fed to the shift input of register 42 and sets the unit to the following (second

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rum) discharge de, wrapped the first discharge of this register. In this case, the next switch key 14 is turned on, and the first input of the comparison unit 15 is supplied with a voltage twice as large as in the previous clock cycle. If this voltage also turns out to be less than the voltage supplied to the second input of the comparison unit 15, then, similarly to that described by the next pulse from the generator 30, the second-bit trigger of register 42 is set to zero, and the next-bit trigger is one. Thus, the device operates until the clock cycle during which the voltage coming from the output of the switch 14 to the first input of the comparison unit 15 will not be; is greater than or equal to the voltage applied to the second input of the comparing unit 15 from the output of the converter 16. When the comparing unit 15 is triggered, its output pulse sets the RS flip-flop 35 to the zero state. The passage of pulses through the element 36 of the generator 30 to the shift input of the register 42 is stopped. In register 42, a negative order code will be fixed. Next, the mantissa code is generated, as with a positive order code.

If during the formation of a negative order code shift, the pulse imposes an additional (t + 1) th register register 42 in the single position, then the RS flip-flops 29 and 35 are set to zero with a high potential from the single output of this trigger. Formation of mantissa codes

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And the order is terminated, since

the input of the converter in this case receives a voltage less than the device allows to convert.

Claims (2)

 “Formula 1. Voltage converter to code containing voltage divider, switch, first comparison unit, code to voltage converter, pulse distributor, register, clock generator, first and second elements AND, first and second elements OR, first, second and third SS TSH1 RS-flip-flops, encoder, first, second and third delay elements, switch, the first output of which is connected to the first input of the first one nivy unit, the second input of which is connected to the output of the code-to-voltage converter, the inputs of which are connected to the corresponding register outputs and are the mantissa code bus, the output of the first comparison block is connected to the register write enable input, the information inputs of which are connected to the corresponding outputs of the pulse distributor, The S input of the first RS flip-flop is connected to the output of the first OR element, the R input is connected to the output of the first delay element, the input of which is connected to the first output of the distributor The pulses, the first input of the first element OR is connected to the output of the first comparison block, the second input is the startup bus, the first output of the clock generator is connected to the first input of the first element AND, the encoder outputs are the order code bus, and the inputs are combined with the corresponding control inputs switch, characterized in that, in order to expand the scope of application by converting voltages of different polarities and simplifying the type of code being formed, the second and third comparing blocks, the fourth and the third RS flip-flop shift register, the third and fourth elements OR, the third and fourth element AND, the fourth delay element, analog switch, voltage multiplier, group of elements OR, voltage module unit, two analog keys, information input of the first analog the key is an input bus, the control input is connected to the second output of the clock generator, and the output of the first analog switch is connected to the input of the module of the voltage module and to the first input of the second comparison block, the second input of which is a common bus, the output of unit modulation voltage connected to the data input. the second analog switch and the first input of the third comparison block, to the second input of which the output of the code-to-voltage converter is connected, the control input of the second analog switch is connected to the forward output of the second RS flip-flop, the output of the second analog switch is connected to the first input of the switch and the information input of the analog switch, the first and second control inputs of which are connected respectively to the direct and inverse outputs of the third RS flip-flop, the first the output of the analog switch is connected to the input of a voltage multiplier, and the second is connected to the input of a voltage divider, the corresponding outputs of a multiplier and a voltage divider are connected via rf to the control unit OR, to the corresponding second inputs of the switch, the control inputs of which are connected to the corresponding outputs group of outputs of the reverse shift register, the first output of the group of outputs of which is connected to the third input of the first OR element and to the first input of the second OR element, you reversing shift register stroke connected to the second input of the second OR element, and to the first input of the third OR element, the last output of the pulse distributor is connected to the second input of the coy, the third input of the second OR element is connected to the output of the first comparing unit, the control input of the shift towards the higher bits reverse shift register combined with the first input of the second element AND and connected to the direct output of the third RS flip-flop and is an order sign bus that controls the shift input in the direction of the lower bits of the reverse shift register combined with the Perz input of the third element And and is connected to the inverse output of the third-third-rs RS flip-flop, the shift input of the reverse shift register is connected to the output of the first element And, the first, the installation input of the reverse shift register is connected to the output of the fourth element OR, the second installation input and the first information input of the reverse shift register, the R-input of the third RS-flip-flop, the installation inputs of the pulse distributor and the register, the input of the second delay element, R- input of the second RS-flip-flop, S-input the fourth RS flip-flop is combined and is a trigger bus; the second information input of the reverse shift register is combined with the first input of the fourth OR element and dinene with the output of the second element And, the third information input of the reverse shift register is combined with the second input of the fourth element OR and connected to the output of the third element And, the second inputs of the second and third elements And combined and through the third delay element connected to the first output of the pulse distributor, the second input of the first element And connected: direct output of the fifth RS-flip-flop, S-input of which combined with the S-input of the second RS-flip-flop and through the fourth delay element connected to the output of the second delay element and with the first input of the clock generator, the R-input of the fifth RS-flip-flop is connected to the output of the second OR element, while the R-input of the fourth RS- trigger The cable is connected to the output of the second comparison unit, and the direct output is the mantissa sign bus, the counting input is distributed five 0 the pulse divider is connected to the output of the fourth element I, the first input of which is connected to the direct output of the first RS flip-flop, the second input is connected to the first output of the clock generator, the S-input of the third RS flip-flop is connected to the output of the third comparison unit. 2. The converter according to claim 1, characterized in that the module of the voltage module is made on two diodes and an inverting amplifier, the input of which is combined with the anode of the first diode and is the input of the block, the output of the inverting amplifier is connected to the anode of the second diode, the cathodes of the first and second diodes combined and are the output of the block, I years g GP W rrfr Good dock