SU1418737A1 - Device for reliability modeling of complex systems - Google Patents

Abstract

The invention relates to computing and can be used in the statistical modeling of complex systems, represented as a probabilistic graph, to determine the quality characteristics, in particular, the indicators of the reliability of the system. The purpose of the invention is to expand the functional capabilities of the device by providing independent parallel modeling of the processes of occurrence of failures. This is achieved by introducing into the device containing the first and second groups of elements 5 and 11, the first and second groups of counters 9 and 12 and the decoder 8, additionally the pulse generator 1, the first 2, the second 3, the third 4 delay elements, TI PI-NOT 6, counter 7, the third and fourth groups of counters 15 and 10, the group of elements OR 13, the third group of elements And 14, the group of generators 16 random signals and the adder 17. 1 Il. With lO with

Description

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The invention relates to computing technology and can be used in statistical modeling of complex systems represented as a probabilistic graph j for determining quality characteristics, in particular, system reliability indicators.

The purpose of the invention is to expand the functionality of the device by providing independent parallel modeling of the processes of occurrence of failures.

The drawing shows a block diagram of the proposed device.

The device consists of a pulse generator 1, delay elements 2-4, p elements AND 5 of the first group, element 6 OR NONE, counter 7, decoder 8, m counters 9 of the first group, t-1 counters 10 of the fourth group, m elements 11 and 11 the second group, m counters 12 of the second group, elements OR 13 groups, t-1 elements AND 14 of the third group, counters 15 of the third group, group of generators 16 random pulses with adjustable duty cycle, adder 17.

The output 18 of the clock frequency of the device is the launch input of the simulated network, the input of the sign of the end of the simulated operation, the network 19 of the device is the output of the end of the simulated network (they are connected to the input of the AND element 5. the first group corresponding to the initial node of the simulated network and the output of the element And 5 of the first group, respectively; its end node of the simulated ceTvi, respectively, the second 20 and third 21 inputs of the device are respectively the start and stop inputs of the generator.

The device works as follows.

Starting the device is performed by applying to the input 20 a start signal of the generator 1. The device operates in cycles each of which will keep clock moments tg,,. At the time of Od, the output of the generator 1 generates a signal, implementing the iTjriii initial setting of the adder 17 to the state corresponding to the presence of a binary code at its output, the number of all elements of AND 5 (the case of the operability of all elements of the simulated system) .. At the moment, the signal

from the output of the element 2, the delays are fed to the input 18 of the circuit representing the simulated system. At this moment, the first inputs of the And 5 elements, which are the model links of the system under study, can receive signals from the generators of 16 random pulses with an adjustable duty cycle,

g These generators simulate the occurrence of failures in system components with a predetermined probability. In this case, the pulse duty cycle is determined from the ratio of

5 P 1-P, which causes the appearance of single impulses at arbitrary time points with probabilities equal to the operational state of the elements simulating the system at the same time point. At the simultaneous occurrence of signals at the first and second inputs of the element 5, a signal is generated at its output, which arrives at the corresponding subtractive input of the adder 17. Therefore, after the signal from the delay element 2 passes through the circuit displaying the system, the code at the output of the adder 17

0 will be equal to the code of the number of elements And 5, the outputs of which did not receive signals to the input of the adder 17, i.e. numbers, failed elements of the simulated system. If all the elements are operable, then the output of the adder 17 will be a zero code, which as a result of the inversion in the OR-NOT 6 element increases the content of the counter 7 by one. Thus,

0 counter-; 7 calculates the number of tests in which all elements of the simulated system are operational. At time T, the output of the delay element 3 appears as the signal of the decoder 8. At this moment, at the output of the adder 17 a nonzero code, the decipher 8 provides its interpretation and generates a signal at one of its outputs corresponding to the number of failed the moment in time of the elements of the simulated system. This signal is fed to the input of counter 9, which counts the number of tests with the corresponding number of failures, to the first input of the corresponding element I.11, and also to the input of the corresponding element lUIM 13 "If at this time point through evil 5

0

five

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ment 4 delays to the second inputs of the elements OR 13 receives a signal from input 19, displaying the system, then the signal from the output of the decoder 8 through the corresponding element 11 will be fixed by one of the counters 12, thereby increasing by one the number of successful circuit tests

P

 one

with the current number of failed items. When the signal passes from the output of the decoder 8 through a set of sequentially connected elements OR 13, signals are formed at the inputs of the counters 10

15, corresponding to 2 p-, provided that K is not less

and elements and

X

tekup (its number of failed elements of the system. If there is an output signal of the circuit delayed by the delay element 4 using the delay element 4 in the second inputs of the elements 15, then the contents in counters 16 will be increased by one

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provided that k is not less than the current number of failed elements of the system. This concludes the first test cycle of the simulated system.

In the subsequent test cycles, the device functions in the same way. The completion of the simulation is carried out by applying to the input 21 of the generator 1 stop signal,

Claims (1)

Invention Formula A device for reliable modeling of complex systems, containing the first and second groups of elements And, the decoder, the first and second groups of meters, characterized in that, in order to expand the functionality of the device by providing independent parallel modeling of the processes of occurrence of failures, a third and a fourth are entered into it groups of counters, first, second and third delay elements, e about ; tick, element OR NOT, group of elements OR, adder, group of random pulse generators, pulse generator, the output of which is connected to the synchronization input of the adder and the input of the first delay element, the output of which is the output frequency of the device and connected 10 through the second delay element with the synchronization input of the decoder, the outputs of which are connected to the counting inputs of the corresponding counters of the first group, the first inputs 15 corresponding AND elements of the second group and the first inputs of the corresponding 51x elements of the OR group, the output of the K-th element of the OR group (K 1, N, where N is the number of nodes of the graph) is 20 with the second input (K + O-th element of the OR group , with the counting input of the K-th counter of the third group and the first input of the K-th element AND the third group, the outputs of the elements And the second 25 groups are connected to the counting inputs of the corresponding counters of the second group, the outputs of the elements of the third group are connected to the counting inputs of the corresponding 1X counters of four 30 of the group, the second inputs of the elements of the second and third groups are connected to the output of the third delay element, the input of which is the input of the sign of the end of operation of the device; logging 40 mi. the adder, the second inputs and outputs of elements AND of the first group are connected in accordance with the graph of the system under study, the output clock of the device is connected to the second input of the AND element of the first group corresponding to the initial node of the graph, the input of the sign of the device’s end corresponding to the end node of the graph, the pulse generator start input is the device start input, the pulse generator stop input is the device stop input. WIIII Order 4155/47 Random polygons pr-tie, Uzhgorod ,, ul. Project, 4 Circulation 704 Subscription