SU1417036A1 - Storage - Google Patents

Abstract

The invention relates to digital computing, in particular to electronics, and can be used in random access semiconductor memory devices. The memory device contains a matrix of 1 memory elements consisting of memory elements L, combined with dictionary 3 and bit 4 buses, row 5 and column 6 decoders, synchronization unit 10, mode setting unit 11, write-read amplifiers 8, main 12 and an additional 13 sampling pulse formers, a reference voltage bus 14, a control unit 15. The storage device has a wide range of variations in the voltage of the power supply and temperature, which is associated with a decrease in sensitivity in the storage device. The introduction of a control unit and an additional pulse sampler makes it possible to increase the reliability of the device when changing the structural and schematic parameters of the instruments. 1 hp f-ly, 2 ill. with (L

Description

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The invention relates to digital computing, in particular to electronics, and can be used in random access semiconductor memory devices.

The aim of the invention is to increase the reliability of the storage device.

FIG. 1 shows a block diagram of a memory device; Fig 2 is a block diagram of the control unit.

The storage device contains a matrix of memory elements t (EP) consisting of EP 2, combined with dictionary 3 and bit 4 buses, row 5 and column 6 decoders, inputs 7 of which are address inputs of the device; - tishan, the first input - output 9 of which is the input / output of the device, synchronization unit 10 and mode setting unit 11, main 12 and additional 13 sampling drivers (FIV), reference voltage bus 14, control unit 15, input 16 and exit 17 of which are connected respectively with the output dopol FIV itelnogo 13 and the input unit 11 setting mode. The first 18 and second 19 outputs of the synchronization unit 10 are connected to the first input .20 of the additional FIV 13 and to the second input 21 of the amplifiers 8 recordings, the third 22 and fourth 23 inputs of which are connected respectively to the corresponding bit buses 4 and to the outputs of the decoder 6 columns. The outputs of the decoder 5 lines and the mode setting unit 11 are connected respectively to the first y 24 and second 25 inputs of the FIV 12, the output of which is connected to the corresponding vocabulary buses 3. The reference voltage bus is connected to the second output 26 of the additional FIV 13

The control unit 15 (FIG. 2) contains a memory element 27, the first input 28 of which is the input of the control unit, the read amplifier 29, the output of which is the output of the control unit, the memory element installation unit 30 whose input is connected to the first inputs 31 of the memory element 27 and the read amplifier 29, the second 32 and third 33 inputs of which are connected respectively to the first 34 and second 35 outputs of the memory element 27, the second input 36 of which is connected to the top

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house node 30 installation of the memory element ..,

The storage device operates as follows.

In the storage mode, at the output of the FIV 12, the potentials are maintained on the vocabulary 3 and bit 4 buses, which provide data storage in the EP 2, the write-read amplifiers 8 are turned off. When accessing the memory, the required EP 2 is selected by turning on the driver 12 and the amplifier 8 corresponding to the input addresses on input 7. In the recording mode, the selected amplifier 8 generates a signal corresponding to the input information, which is then recorded in the selected EA 2. In the read mode, the signal generated in the wake of 4 is amplified and outputted to 9 memory; Address decoders 5 lines and columns 6 ensure that FIV 12 and amplifier 8 are turned on in accordance with the input address signals. The synchronization unit-10 synchronizes the operation of the storage units, controls the operation of the storage unit.

The correct operation of the charger when reading depends on the parameters of the signals generated by the FIV 12, primarily the amplitudes. Under certain conditions, for example, when the voltage of the power source deviates from the nominal value, the memory may malfunction (e.g., false reading). In such cases, the control unit 15, to the input of which a signal from the output of the FIV 13 arrives, and the mode setting unit 11 thus regulate the operation of the FIV 12, which ensures reliable reading of information from the memory. The signal from the first output of the synchronization unit 10 is supplied to the first input 20 of the FIV 13, having characteristics identical to the main FIV 12, the second input 26 of the FIV 13 is connected to the reference voltage terminal 14, the potential of which is determined depending on the signals specified by the FIV 12 in normal conditions As a result, at the output of the FIV 13, a signal is generated that has characteristics similar to those of the signals produced by the main FIV 12, if there were no control unit 15 in the memory. The signal from the output of the additional FIV 13 is fed to the input 16 of the control unit 15, at the output 17 of which a signal is formed with parameters depending on whether

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whether or not the parameters of the sampled signals at the output of the main FIV 12 are reliable performance of the memory. Depending on the parameters of the signal input to the block 11 from the output 17 of the control 15, the output of the block 11 forms a signal that changes the parameters of the sampling pulses and ensures reliable operation of the charger.

The introduction of an additional FIV 13 and control unit 15 makes it possible to increase the reliability of the memory by reducing the sensitivity to variation of parameters, the deviation of the voltage of the power source from the nominal value, which also expands the allowable range of variation of the power voltage of the charger.

The control unit 15 operates as follows.

In the storage mode, the input 16 of block 15 is supplied with an logical logic signal, the read amplifier 29 is disabled, the EA installation unit 30 sets the memory element 27 to a certain state, in which false reading is most likely due to internal imbalance of the parameters of the memory elements. The output 17 of block 15 maintains a signal with a low logic level. In the read mode, the input 16 of the block 15 comes from the synchronization block 10, having a high logic level, which connects the EA 27 to the read amplifier 29, which is turned on, and the EA installation unit 30 is turned off at the same time. As a result, a read signal is generated at the output 17 of block 15, the parameters of which depend on whether a false read has occurred or not. The parameters of the input signal to the input 16 of the unit 15, the memory element 27, the read amplifier 29 track the characteristics of the signals and the parameters of the circuits using the Mfccc in the EF matrix 1, which allows monitoring and increasing the reliability of the memory.

The introduction of a COLTROL unit that monitors the operation of memory elements of the charger makes it possible to increase the reliability of the charger when changing the counter-circuit-technical parameters of the instruments.

Additional FIV 13 can be performed similarly to FIV 12. As the decoder of rows 5 and columns 6 and also the synchronization unit 10 can

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known logical blocks should be applied.

The proposed storage device has a wider range of variation, voltage of the power supply and temperature, which is associated with a decrease in sensitivity in the storage device. The introduction of additional blocks in the memory does not lead to a deterioration of the Q speed and power consumption of the memory, a significant increase in the number of components (transistors, etc.) of the memory. -.

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Claims (2)

1. A memory device containing a matrix of memory elements, row and column decoders, inputs Which Q are address inputs of the device, record-read amplifiers, the first inputs-outputs of which are combined and are information input-output of the device, synchronization syn5 block, mode setting block, sampling drivers, the first and second inputs of which are connected respectively to the outputs line decoders and mode setting block output, 0, the second output of the synchronization unit is connected to the second inputs of the write-read amplifiers, the third and fourth inputs of which are connected respectively to the corresponding bit chips of the matrix of memory elements and the outputs of the column decoder, the outputs of the sampling drivers of the pulse elements are memory, characterized in that, in order to increase the reliability of the device, it contains an additional sampling pulse shaper. and a control unit, the input and output of which are connected respectively to the output of the additional pulse shaper and sample entry mode specifying unit, a first input of the additional pulse shaper is connected to the sample s e tires reference voltage device, the second input - to the first input of the synchronization unit. 2. The device according to claim 1, wherein the control unit contains a memory element whose first input is the input of the control unit, the read amplifier, the output of which is the output of the control unit, the element installation unit five 0 514170366 the memory, the input of which is connected to the first and second outputs of the element, the input inputs of the memory element and the amplifier, the second input of which is connected to the readout, the second and third inputs to the output of the installation node of the element of the connection are connected with mi ti 36 J6 28 32 33 nineteen 17 FIG. 2