SU1411985A1 - Radio communication system with access on request - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to reduce the time of message delivery. The system contains a central station (CA) and p, transceiver stations (PPP). Information packets arriving at the CS from PPP at frequency f are demodulated and recorded. Requests from the PPP are transmitted in the total frequency band uf, where channel separation (PPP) is used according to the waveform. From the group signal, requests from each PPP are selected in accordance with its address signal. Further, according to a predetermined algorithm, requests are processed, the time of output of the information packet from the PPP is calculated, and a response packet is formed, which is transmitted on frequency i. PPP are in receive mode at frequency f. After receiving an information packet whose address matches the PPP address, it is registered and the PPP switches to frequency f. When information is generated, the volume of the information packet is counted and the coded request is emitted in channels {in the frequency band uf. Upon receipt of a response from the CA, the information packet is radiated at. the channel at the frequency f- "and at the end of the packet the PTS switches to the frequency f. The goal is achieved by ensuring the transfer of information between the PPP and the CA at separated frequencies, 6 Il. -o 1X (L

Description

The invention relates to radio engineering and communications, and can be used in the transmission of information between receiving and transmitting stations (BTS) and a central station (DS) at separated frequencies.

The purpose of the invention is to reduce the time of message delivery.

FIG. 1 is a block diagram of a central station; in fig. 2 is a block diagram of a response generation unit: in FIG. 3 is a block diagram of a transceiver station; in fig. 4 is a block diagram of the query generation unit; FIG. 5 shows the message format: request from PPP a), response from the CA b), information packet c), pa FIG. 6 - algorithm for processing requests in the block I / o request signals.

A radio access system with access on request contains a receiving station 1, receiver 2, demodulator 3, block 4 registrars at the central station

data, transmitter 5, split channel unit 6, modulator 7, switch 8, query signal input / output unit 9, switch 10, generation response unit 11, subtraction unit 12, timer 13, transmit antenna 14.

The block 11 forwards the response, contains a register forming 15, a generator 16 of the first marker, an address register 17, a generator 18 of the ending signal, a differentiating chain 19, a delay line 20.

At the transceiver station, the system (FIG. 3) contains an antenna 21, a receiver 22, a transmitter 23, an additional transmitter 24, a demodulator 25, a modulator 26, an additional modulator 27, an encoder 28, a pseudo-noise signal generator 29 (PSH ), the decoder 30 of the first marker, the first buffer register 31, the block 52 forming the request, the counter-to 33, the first 34 and second 35 decoders, line 36 delay, block 37 data, the decoder 38

the second marker, the third 39 and the fourth 40 decoders, the first element And 41, the inverter 42, the second element And 43, the second bead register 44, the block 45 of the data recording, the transmitting antenna 46.

The query generation unit 32 comprises the formative register 47, the zero marker generator 48, the address generator 49, the window signal generator 50

Q 5 0

five

O

Q 5

five

Chani, di (}) endow chain 51 and delay line 52.

The system (Fig. 1) works as follows.

The incoming signals at the frequency f (information packets from the PPP) from the receiving antenna 1 and receiver 2 are demodulated by the demodulator 3 and fed to the data register 4. Requests from the PPP are transmitted in the common frequency band uf, where channel separation (PPP) is used according to the waveform. From the second output of the demodulator 3, the group signal (requests) enters the channel separation unit 6, where requests from each PPP are allocated in accordance with the address signal of the PPP. Switch 8 polls the outputs of the channel separation unit 6 and sequentially enters the requests into the input register of the block channel 9. The latter processes requests in accordance with the algorithm (Fig. 6). In RAM block 9, an array of M (j, t: t) and constants c, b, and cf are stored, where j is the number of the PPP; с- - volume of the information package specified in the request: tj | - the time of the withdrawal of the information packet from the PPP that sent the request; c is the data transmission rate over the communication channel at the frequency I f i ff the time required for entering synchronization; с „- time of signal propagation along the CA line - PPP. When an i-ro request appears in the selector channel, the field reads the volume of the Vt message and calculates the value of T; V; / c, which is entered into the corresponding line of the array M (,, О). After the preparatory operations, the time of output of the information packet from the PPP is calculated.

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max + el,

Q 45

50

55

where is the latest time

output of an information packet from queued and sent a request to PPP.

After the output of the next response packet, the algorithm provides for a search in the M array of the nearest tgnel Mw output time — taking into account the propagation time tp, the output time of the information packet from the TPS is calculated. This time is written to the output register.

The selector channel and the channel through the switch 10 enters the subtraction unit 12, where the current time is compared (from timer 13) and time t. When the times are equal, the subtraction unit 12 generates a single signal that is fed to the control input of the selector channel, and the output of the address of the PPP to the output register is initiated. Under the action of the control signal, the switch 10 operates on the second output and the address of the PPP enters the response generating unit 11, which forms the response packet. The response packet then goes to the modulator 7, the transmitter 5 and the transmitting antenna 14 and is transmitted on the frequency

fi.

Block 11 forming the answer

(Fig. 2) works as follows.

When the address arrives, it is recorded in the address register 17. At the same time, through a differentiating chain 19, a start signal is generated for the generators of the first marker 16 and the end signal 18, which force the corresponding signals into the forming register 15. The start signal through the delay line 20 (taking into account the time of signal generation and writing to the forming register) is fed to the read control input Forming register 15,

The transceiver station (Fig. 3) operates as follows.

ShTS are in receive mode at frequency f. After passing the signals through the receiving antenna 21, the receiver 22 and the demodulator 25, an information packet arrives at the decoder 38 of the second marker and then to the third decoder 39 of the termination signal, the fourth decoder 40 of the address signal and the input of the second element And 43. If the packet address matches the address PPP, the second element And 43 passes the packet to the second buffer register 44, and the inverter circuit 42 - the first element And 41 generates a signal Record. After the reception of the packet from the output of the third decoder 39 is completed, a read signal is generated for transmitting the recorded information packet to the data acquisition unit 45 and switching the receiver 22 to the frequency f. Block 37 vdachi data upon the occurrence of information generates and transmits an information packet in the first buffer

register 31 (under the influence of the signal Record from the output of the delay line 36). At the same time, the counter 33 counts the volume (number of bits) of the V-, information packet. The calculated value enters the block 32 fop p poBANi request. The request is encoded in the encoder 28 by a noise-like signal, which is generated by the generator 29 FIJJC, and through the additional NfOAyaHTop 27J the additional transmitter 24 and the transmitting antenna 46 are radiated to the channel in the frequency band d.

5 CA through the deitfrater 30 of the first marker and the first dec1frator 34 signal arrives at the input of the first buffer register 31. Next, the information packet goes through the modulator module 26, the transmitter 23 to the transmitting antenna 46 and is transmitted into the channel at the frequency. The second signal 35, on the signal of the packet end one, generates a control signal for switching

5 receivers 22. On frequency f.

The query generation unit 32 operates in the following manner. (Fig. 4).

The counter 33 brings to the first input of the forming register the value of the message volume. This signal passes through a differentiating chain 51 and is triggered for zero mark generators 48, address 49 of the ending signal -50. Delay line 52 serves to delay the control signal Read at the request generation time.

Claims (1)

Formula Invention 0 Radio access system with access request, containing a central station consisting of a serially connected receiving antenna, receiving g of the nickname, demodulator and data acquisition unit, serially connected — the response unit of the modulator, transmitter and transmitting antenna, as well as the subtraction unit, ii transceiver Q stations consisting of the serially connected receiving antenna, receiver and demodulator, serially connected the data transmission unit, the first bu er register pa, the modulator, the transmitter and the transmitting antenna, are sequentially connected to the first decoder of the delay line, the output of which is connected to. the second input of the first buffer region 514 country, the second decoder sequentially connected to the third decoder, the inverter, the first element I, I of the second buffer register and data recording unit, the fourth decoder, the output of which is connected to the second input of the first element And and the first input of the second element And, the output of which is connected to the second input of the second buffer register, and the output of the first decoder is connected to the input of the second decoder and the third input of the first buffer register, the output of the inverter is connected to the second input of the second element And, the output retego decoder coupled to the third input of the second buffer register, characterized in that, to reduce the delivery time soobsche1sh, administered on. the central station are connected in series by a channel separation unit, a switch, an I / O block of the interrogation signals and a switch, a timer, the output of which is connected to the first input of the subtraction unit, the output of which is connected to the second input of the interrogation block I / O signals and the second input of the switch connected to the second input of the block 5 6 By subtracting, the second output of the switch is connected to the input of the response shaping unit, the auxiliary output of the demodulator is connected to the input of the block; channel separation, at each transceiver station - serially connected pseudo-noise generator, encoder, additional modulator and additional transmitter, the output of which is connected to the auxiliary input of the transmitting antenna, a serially connected counter and a query generation unit whose output is connected to the second input of the encoder, a decoder of the first marker and a decoder of the second marker, while the output of the demodulator is connected to the input of the DS1 generator of the first marker whose output connected to the input of the first decoder, the output of the demodulator is connected to the input of the decoder of the second marker, the output of which is connected to the inputs of the third and fourth decoder and the third input of the second And, the output of the second decoder is connected to the second input of the receiver, and the output of the third decoder is connected to the third input of the receiver, the output of the data block is connected to counter input. Phie.1 Fiz. fl x ftpMpMt Mreslinc OheM weave {End signal FIG. five The beginning Array array M (j. ,,) Record non st st C, CsA, S RAM