SU1405056A1 - Random number generator - Google Patents

Abstract

The invention relates to a computing technique and can be used in attachments to universal PCs for obtaining random numbers that are subject to the Pearson distribution laws. The purpose of the invention is to expand the scope of application by forming random numbers that are subject to the laws of the Pearson distribution. The generator contains a sensor 1 of uniformly distributed random numbers, a block 2 for adding and subtracting, a block of 3 multiplications, a block of 4 memory, a block of 5.control, three groups of 6, 7, 8 OR elements, three elements of 9-11 OR, a delay element 12 and two registers 13, 14. The goal is achieved by introducing new blocks with appropriate functional connections. 1 dw., 2 tab.

Description

four

ABOUT

SP

about ate

The invention relates to computing and can be used in consoles to universal electronic computers for obtaining random numbers obeying the laws of the Pearson distribution.

The purpose of the invention is to expand the scope of application by forming random numbers that are subject to the laws of the Pearson distribution.

The drawing shows a block diagram of a random number generator.

The generator contains a sensor 1 of uniformly distributed random numbers j block 2 of addition and subtraction, block 3 multiplication, block 4 of memory, block 5 of control, groups 6-8 of elements OR of elements OR 9-11, element 12 of delay, registers 13 and 14.

The control unit 5 contains the element OR 15, the counter 16, the decoder 17, the elements OR 18-27, the elements AND 28-30, the element OR 31, the element 32-35 of the delay, the element NOT 36, the element OR 37, the triggers 38-40.

The generator works as follows.

The sequence of operations is given in table. one ,

The register 13 records the code of the sign of the distribution law (the codes for the ad- ministration of the values are given in Table 2), and the signal on the input of the Generator Start 1 starts its operation. The attribute of the distribution law and the code determined by the state of the flip-flops 38-40 determine the address of one or another value stored in memory block 4.

Under the influence of the trigger signal, code 0001 is set in the counter 16, a signal appears on the first output of the decoder 17, which triggers the sensor 15 and also sets the triggers 38-40 to the state 001. The signal from the first output of the decoder also passes through the OR elements 18 and 22 to memory block 4 and starts it to read the value F (ha) for distribution, for example, 1. The value F (t) from block 4 is entered into block 2 by the signal from the first output to block 2 through the element 32 delays and element OR.

The operation of sensor 1 is completed by the occurrence of the cjjy4ai iHoro number on its information output. Cf number 0

five

0

five

0

five

0

0 5

The signal from the output of the formation of the numbers of sensor 1 also sets in counter 16 a code 0002. At the second output of the decoder 17, a signal appears that triggers block 2 through the OR 25 element to perform subtraction.

At the same time, by this signal, the triggers 38-40 are set to the state 002, from block 4 it is read / b2 and entered into block 3.

After the subtraction is completed, the output of the subtraction A is entered into block 3. The signal from elements 28 and OR 21 triggers 38-40 are set to state 003, the block 4 of memory is started with a signal from delay element 33 and the result of subtraction is also written to it. .

The signal from the output of the end of the addition and subtraction of block 2 establishes code 0003 in the counter 16. Under the action of the signal from the third output, block 3 is triggered, triggers 38-40 are set to state 004, /4 is read from block 4 and entered into block 2.

The result of multiplying Z, by the signal from the output of the multiplication end of block 3, is entered into block 2. Now the signal appears at the fourth output of the decoder 17 and starts block 2 to perform an add operation through the element OR 31. At the same time, the triggers 38-40 are set to state 003 , from memory block 4 is read /, and entered into block 3.

After operations by block 2, the result Z under the action of the signal from the output of the end of the addition and subtraction of block 2 is entered into block 3. In counter 16, the code 0005 is recorded. The signal from the fifth output of decoder 17 is started up by block 3.

The result of the multiplication of Z-i is entered again into block 3 by the signal from the output of element AND 29. From delay element 35, the signal passes through element OR 22 to block 4 and starts it to read. The read out is entered in block 3. The signal from delay element 32 sets the triggers 38-40 to state 004, and in counter 1 6 the code 0006 (since the signal is decrypted at the fifth output and 17 is -1 signal, then the output is NOT 36 - low level and it closes the element OR 37).

The signal from the sixth output of the decoder 17 starts the block 3, and also sets the triggers 38-40 to the state 005. From block 4 is read and entered into block 2.

After multiplying, Z is entered into block 2. In counter 16, code 0007 is set. The signal from the seventh output starts block 2. At the same time, triggers 38-40 are set to state 003, from block 4 it is read out D and entered into block 3.

The result of subtracting Zj is fixed in block 3. The signal from the output of the addition and subtraction of block 2 causes a signal at the eighth output of the decoder 17, which triggers Vlok 3, triggers 38-40 are set to state 006, from block 4 it is read m and entered into block 2 .

After multiplying, Z is also entered in block 2,

The signal from the ninth output of the decoder 17 starts the block 2 to perform the addition operation. Triggers 38-40 are set to state 007. The result of the add operation is stored in memory block 4. At the tenth output of the decoder 17, a signal appears that records the generated number in register 14, the output of which is the generator output.

The essence of the invention is as follows.

Known that the equation

-GHB; B: “.

where b- (, 1,2) - parameters

m is the distribution mode, is the Pearson equation.

Dependencies that define the relationship between-b. and parameters of approximating distribution, have the form, 1, S + 2

Bo - si2; - -G S-2

B - A 1 b, - - 6 - where S iiill irlA. 3.1-2p, + 6

 central moments of k-ro

for now.

In practice, when approximating empirical distributions,

the first four points and, using expressions (2), determine the parameters of the Pearson equations. Using a row of views

, .)one,. .

l) goVI1Hr

And ratios

ten

15

(3)

etc. An algorithm can be developed to overcome the difficulties of directly simulating a distribution institute approximated by Pearson curves. Since the distributions are given by the differential equation (1), and the boundary conditions F (-os) O, F (SI) 1, then from formulas (3) and the system

F (Xm) o,.)

 (x), f (x), o

35

follows that

D x

40

D x

X,

 ABOUT,

D3

1 Li5 "l

45

50

etc.

Choosing as a reference point Xy t, you can get

F (x) I GI2IS (x)

 o- dx L hox2 + b, x + c

F (ho),

one

box | + b,

v4 (-7v rv) 2HO.

55 F (x,) - 2F (- (, x, -eb) 2

(four)

This determines the structure of the simulation algorithm, which provides an imitation of the Pearson distributions

X (-F (m) j 7

1 W-F (m) F (m)

3

F CmXbomVb m + b)

(five)

(m) T 2 (2bom + b i)

4 (bpm + bim + b, 2) 2FMm)

If we denote (pre-calculated constant coefficients)

1 P o,

R

6F (t) ()

2bom + bi

12F (m) () 1

fi --- 1

F (m)

the relationship (5) is converted to

 () where Л о (- F (m).

Claims (1)

Claims i A random number generator, the content of a sensor of uniformly distributed random numbers, that is, with the aim of expanding the field of application through the formation of random numbers, obeying the laws Pearson distribution, it contains a memory unit, an addition and subtraction unit, a multiplier unit, three groups of elements OR, three RSHI elements, a delay element, a control unit that includes thirteen 1PI elements, a counter, a decoder, a NOT element, four delay elements, three triggers , three elements And, n Using the output of the first OR element of the control unit is connected to the counting input of the counter, the output of which is connected to the input of the detector, the first output of which is connected to the sensor start input of uniformly distributed random numbers, the second output of the decoder is connected to the first inputs of the second and third OR elements and the output of which is connected to the first input of the fourth OR element, the code of which is connected to the input of the installation in O of the first trigger, the output of which is connected to the first address input of the memory unit, the third the output of the decoder is connected to the first input of the fifth element OR, the output of which is assigned to the input of the start of the block, the fourth output of the decoder is connected to the second input of the third ITSH element, the output of which through the first delay element is connected to the first input of the multiplier unit, the fifth output of the decoder is connected to the first input of the second I element, the output of which the second delay element is connected with the first input of the sixth OR element, the output of which is connected to the read input of the memory unit, the sixth output of the decoder is connected to the second input of the fifth OR element, the third input of which is connected to the fifth output of the decoder and through the element is NOT connected to the first input of the seventh element OR, the output of which is connected to the first input of the first element OR, the second input which is the generator Start input, the seventh output of the decoder is connected to the second input of the second OR element, the output of which is connected to the resolution input of the adder unit and subtracting, the eighth output of the decoder is connected to the fourth input of the fifth OR element and connected to the second input of the sixth OR element, the third input of which is connected to the fourth output of the decoder and connected to the second input of the fourth OR element, the third input of which is connected to the fourth input of the sixth OR element, the third input of the third OR element and is connected to the seventh output of the decoder, the ninth output of which is connected to the first input of the eighth OR element, the output of which is connected to the input of setting the mode of the adding and calculating unit Tanya, the output of the ninth element OR is connected to the fifth input of the sixth element OR and connected to the first input of the tenth element OR, the second input of which is connected to the third input of the first OR element and connected to the output of the third delay element, whose input is connected to the output of the second element delays, the first, second, third, fourth and fifth inputs of the ninth element OR are connected respectively to the first, second, third, sixth and ninth outputs of the decoder, the eighth output of which is connected to / installation in 1 of the first input installation in the second O and, 11 1405056 trigger and elements triggers gera, the installation input in is connected to the first input of the eleventh OR element, the output of which is connected to the “1” trigger input, the output of which is connected to the second address input of the memory unit, the third address input of which is connected to the forward output of the second trigger, the counting input of which is connected with the output of the tenth OR element, the output of the fourth delay element is connected to the first input of the twelfth OR element, the output of which is connected to the write input of the memory block, the second input of the twelfth OR element is connected to the output of the third element And, first the input of which is connected to the ninth output of the decoder, the second input of the third element I is connected to the second input of the first element AND, the fourth stroke of the first element OR and the output of the end of the addition and subtraction of the addition and subtraction unit, the fifth turn of the first element OR is connected with the output of the sensor number formation of uniformly distributed random numbers, the second input of the second element AND is connected to the second input of the seventh OR element and connected to the output of the multiplication unit multiplication end, the first output of the decoder OR is connected to the first input of the thirteenth OR element, the output of which is connected to the first recording input addition and subtraction unit, the second input of the thirteenth element OR is connected to the output of the end of the operation of the intelligent block, the second input of the eighth element OR is connected to the fourth input of the decoder a, the information bit outputs of the sensor of uniformly distributed random numbers are connected to the first outputs of the corresponding elements OR of the first group, the second inputs of the I.G1I elements of the first group are connected with the corresponding bit outputs of the memory block, the first group of information inputs of the multiplication unit with the first inputs of the corresponding ten 15 20 25 thirty 35 40 45 50 the element is equipped with the corresponding information and the second group of inputs of the informational memory unit is read out; the second group of information of the block decoder is not first OR, the output of the second el The output of the sensor output case of the first electric output, the output of the reading block is connected to the element I and the second and second element, the fourth hell connected by the output of the formation input back of the memory generator, register with decoder eight items five 0 five 0 five 0 five 0 ISH NOROY GRUPSH 1, OUT1: YES element} OR the first group is associated with the nepi oii correspondence by the group of information input block and subtractor, the outputs of the second group OR of the second group are connected to the corresponding second group of the input and subtraction block, the information bit outputs of which are connected to the cooTBTCTxxxxxxxpx unit of the addition and subtraction unit, the informational outputs of the second group are connected to the corresponding section of the x and x unit. the bit inputs of the memory block and the first inputs of the corresponding elements I.Sh of the third group, the second inputs of the elements OR t of the group are connected to the corresponding information bits of the output By the multiplier unit, the third output of the decoder of the control unit is connected to the first input of the first OR element, the output of which is connected to the first input of the second OR element through the delay element, the output of which is connected to the second input of the addition and subtraction unit, the second input of the second OR element is connected to the output ending the formation of the sensor numbers of uniformly distributed random numbers, the second input of the first element OR is connected to the sixth output of the decoder of the control unit, the output of the end of addition and subtraction of the layer block The second input of the third element OR is connected with the output of the second element AND of the control unit, the fourth, fifth, sixth and seventh address inputs of the memory block. connected to the corresponding bit outputs of the first register, the information input of which is the input of setting the generator distribution law; the bit outputs of the memory unit are connected to one -1 variable bit inputs of the second register pa, whose output is the output of the generator, the second register clock input connected to ten. output of the decoder control unit. Table 1 d o (-F (m) Ai X 1 + Z,, AI Z, f, -Z m + z  2, Z, Z X Distribution Code address of the value F (m) J l J L 1 1 ™ 1 2 3 4 5 6 7 8 9 0 11 12 0001001 0010001 0011001 0100001 0101001 0110001 0111001 1000001 1001001 1010001 1011001 1100001 0001010 0010010 0011010 0100010 0101010 0110010 0111010 1000010 1001010 101001.0 1011010 1100010 0001011 0010011 0011011 0100011 0101011 O1100 l1 0111011 1000011 1001011 1010011 1011011 1100011 F (m) P Ai D. 2 3 m table 2 X 0001101 0010101 0011101 0100101 0101101 0110101 0111101 1000101 1001101 1010101 1011101 1100101 0001110 0010110 0011110 0100110 0101110 0110110 0111110 1000110 1001110 1010110 1011110 1100110 0001111 0010111 0011111 0100111 0101 111 0110111 0111111 1000111 1001111 1010111 1011111 1100111