SU1394376A1 - Device for controlling a group of n fanned-out thyristor converters - Google Patents

Abstract

The invention is intended to organize a system for supplying power to mass consumers, for example, workshops, plots, energy-intensive equipment, at frequencies different from the generally accepted frequency of 50 Hz, and adjustable frequencies. The purpose of the invention is to reduce the installed power of the power equipment by eliminating the reactive power compensation link from each converter and increasing the energy performance of the power supply system by quickly changing the operating modes of the thyristor converters as the load changes. The effect is achieved due to the fact that the group of n parallel frequency converters additionally includes an active sensor and a load reactive power sensor, two analog-digital converters, two computational units, a scanning unit, a logic unit, a mode memory unit, a constant coefficient unit. , control unit and clock generator, connected in such a way that, depending on the size and nature of the load, the required number of converters are promptly transferred to one of the three Mode: inversion, compensation or allowance. 6 hp f-ly, 12 ill. с (Л со со 4;: а СО v vj ot

Description

eleven

The invention relates to converter equipment and is intended to organize a power supply system of various types of mass consumers (for example, workshops and factories) at frequencies that are usually different from general industrial using thyristor converters.

The purpose of the invention is to reduce the installed power of the power equipment and increase the energy characteristics of the power supply system consisting of n converters connected to a common output network.

Fig. 1 shows a functional diagram of the device for controlling together with a group of thyristor converters in Fig. 2 a diagram of a group of thyristor frequency converters TOTbij in Fig. 3 — the first and second computational blocks; in Fig. 4 — the scanning unit and the node. control) in FIG. 5 — logical block} in FIG. 6 — mode memory block J in FIG. 7 —the algorithm of the operation of the control device — in FIG. 8, the timing diagram of the control unit; Fig. 9 shows a time diagram for converting a converter from a reserve into an inversion mode; Fig. 10 shows a time diagram for converting a converter from an injection mode to a reserve in Fig. 11; a time diagram for converting a converter from compensation mode to a reserve in Fig. 12 is temporary. conversion diagrams of the converter from the reserve to the compensation mode.

The device contains sensors 1 and 2, respectively. Active P and reactive Q load power, connected to the output network of a group of thyristor converters 3j analog-to-digital converters 4 and 5, whose inputs are connected to the outputs of sensors 1 and 2, respectively. Output analog-to-digital converter 4 connected to the information input of the computing unit 6 and the first information input of the computing unit 7, the second information input of which is connected to the output of the analog-digital converter 5. The output of the computer unit 6 is coupled to first inputs 8 and 9 are diagrams comparing and the output of the computer unit 7 is connected to the first inputs of the circuits 10 and 11 of the comparison. A block of 12 constant coefficients output for a constant co

0

five

five

Q 35

the efficiency / P (nominal power of the inverter) is connected to the input of the input code of the constant coefficient of the computing unit 6, and the outputs for the constant coefficients 4Q (nominal power of the compensator) and tg / i (tangent of the blocking angle of the thyristors) to the corresponding inputs of the input of the constant codes coefficients of the computing unit 7. The second inputs of the comparison circuits 8-11 are used to enter the codes of the constant coefficients, respectively, Р ,, (ЛР + Рр), (/ JQ + Q,) and Qg, and are connected to the corresponding outputs of the block 12 (Р, и reserves by total nominal capacity and included inverters and compensators, respectively).

The outputs of the comparison circuits 8-11 are connected respectively to the enable inputs of the inverters, the enable switches off the inverters, the enable switches off of the compensators, and the enable switch on the compensators of the logic unit. 13. Logic unit 13 with four p-bit buses used for transmitting signals (a, -Va), (b, fb), () and () orders for changing the operating modes of thyristor converters, is connected to the recording inputs of memory block 14 modes. In addition, the bus, transmitting the signals for turning on the inverters through the input element OR 15, is connected to the metering input of the inverter of the computing unit 6, the bus transmitting the signals to turn off the inverters through the p input element of the OR 16, is connected to the metering input of the inverter of the computing unit 6, the bus that transmits the signals of the orders for switching on the compensators through the p-input element ISH1 17 is connected to the metering input of the switching on of the compensator of the computing unit 7, and the bus serving for sending the signals of the orders to not e compensators through n-input OR gate 18, connected to the output compensator accounting disconnecting computing unit 7.

Block 14 of the memory modes of the thyristor converters with three n-bit buses used for signal transfer (), (),

() identification of operation modes of thyristor converters, associated with logical 0 logic inputs

40

45

50

Koi o of block 13. The control to cis Hbixci i of block 14 for signals (15, гВ „) n (С, - С) is associated respectively with switch-on-off control passes in-. of inverters and switching-on-off of compensators of the group of 3 thyristor converters.

Output control unit 19 for the first control signal is connected to the Start inputs of analog-to-digital converters 4 and 5, and output 21 for the second control signal to the inputs of the resolution to calculate the functions S and S of the computing blocks 6 and 7. i

The outputs 22 and 23 of the control unit are used to transmit the third and fourth control signals and are connected respectively to the Start and Reset inputs of the scanning unit 24. 20

The clock generator 25 is connected to the synchronization inputs of the recording of the mode memory block 14 and the synchronization input of the control unit 19, the inputs 26 and 27 of which are respectively the 25 start and reset inputs of the control device,

The outputs of scan block 24 are connected to the scanned inputs of logic unit 13. The outputs of elements 15-18 and the last output of block 24 scan are connected through the OR 28 element to the input Stop of scanning stop block 24 and the enable output of the fourth control signal of control unit 19. five

The mode memory unit 14 has inputs 29 for manually setting the operation modes of the thyristor converters. Inputs 30 and 31 of computational units 6 and 7 are used to enter the codes Schr Rccr-KpdQ, respectively (Sho, K. the initial number of included inverters and compensators, respectively, QC is the reactive power of the switching capacitors).

The group of thyristor converters 3 (Fig. 2) is a series of output thyristor converters 32 connected, each of which includes series-connected constant voltage controller 33 with a phase-pulse control unit 34 having a control input 35, LC- filter 36, thyristor. a bridge 37 with a control pulse shaping unit 38, a reactor 39 in the power supply circuit and a battery 40 switching capacitors at the output, as well as a diode

45

Q

0

five

five

five

41, iodkl chennyy to the flue of the bO filter 36 in a non-central direction in terms of) to the supply voltage of the thyristor bridge 37, and the phase-shifting unit 42 connected to the input of the control pulse shaping unit 38 and also having 43 shift control and sync input 44. The synchronization inputs of all nodes 42 are connected to the output of the master oscillator 45.

Computing unit 6 calculates the value of the function.

S, rn and R - R,

where S, is the code at the output of block 6;

pg - number of inverters included in the current time P - rated power of the inverter P - current active power

load.

To calculate this function, the computing unit 6 contains (FIG. 3) a combinational adder-subtractor 46, a combinational subtractor 47, a register 48, a two-input element OR 49 and a two-stage register 50. The output of the register 50 is connected to the first information input of the subtractor 47 and the first information input sum - torus subtractor 46, the second information input of which is the input to the computing unit 6 of the constant coefficient code P from the 12 constant coefficient block, and the output is connected to the input of register 50, setup input 30 which is used to enter into the computing unit 6 the code of the initial power value of the included inverters, and the reception enable input is connected to the output of the OR-49 element. The output of the subtractor 47 is connected to the output of the register 48, the output of which is the output of the computing unit 6, the information input of which is the second information input of the subtractor 47. The receive input of the register 48 and the enable input of the subtractor 47 are combined and form the enable input of the computing function of the computing unit 6. resolving the summation of the adder-subtractor 46 is connected to the first input of the element OR 49 and serves as an input to the inclusion of the inverter (translation of the thyristor converter into the inverter mode)

computing unit 6. The subtraction resolution input of the adder-subtractor 46 and the second input of the element OR 49 are combined and form the inverter turn-off accounting entry (conversion of the converter to the reserve) of the computing unit 6.

Computing unit 7 calculates the function values.

Sj (Q + P tg / iH) - () ,.

where S is the code at the output of the computing unit-, Q is the current reactive load power i

p „is the angle of the thyristors being locked at the nominal load of the transducer; Q. - reactive power of

tampering capacitors; J - the number of compensators currently switched on; aQ is the nominal power of the compensator. To calculate this function, block 7 contains (FIG. 3) a combination adder-subtractor 51, a multiplication unit 52, a combination adder 53, a combination subtractor 54, a register 55, a two-input element OR 56 and a two-stage register 57. The first information input of the subtractor 54 is connected to the output register 57 and the first information input of the subtractor 5 1, the second information input of which is intended to enter the code of the constant coefficient dQ. The output of adder-subtractor 51 is connected to the input of register 57, the set input of which is input 31 of block 7 for entering the initial value code (), and the input enable input is connected to the output of element OR 56. The second information input of subtractor 54 is connected to the output of the adder 53, the first input of which is the second information input of the computing unit 7, and the second input connected to the output of the multiplication unit 52, the first input of which is the first information input of the computing unit 7, and the second input is used to enter the constant code This coefficient tg | b. The input of the summation of the accumulator adder 51 is connected to the first input of the element IL 56 and is the input of the metering of switching on the compensator of the computing unit 7

The subtraction enable input of the subtractor 49 is connected to the second input of the OR element 56 and is the counting input of the compensator of the computational unit 7. The output of the subtractor 54 is connected to the input of the register 55, the output of which serves as the output of the computational unit 7. the enable input of the calculation of the function of the computing unit 7 and is connected to the enable input of the register 55.

Scanning unit 24 (Fig. 4) contains a distributor 58 of pulses per Sn outputs for signals A, -A. The output of which is connected to the synchronization input of the distributor 58, and the first input is connected to the clock generator 59. The second input of the element 61 is connected to the output of the element HE 60, the input of which is the input of the stop of the scan stop and the EC of the distributor 58 and the third input of the element And 61 serve as inputs for the Reset and Start of the block 24, scans an.

The control unit 19 contains (FIG. 4) two-stage RS-triggers 62 and 63. And two-input elements AND 64-69. The RO inputs of the flip-flops 62 and 63 are combined and form the input 27 Reset of the control unit 19. The direct output of the trigger 62 is connected to the first inputs of the elements 64 and 65, and the inverse output to the first inputs of the elements 66 and 67. The direct output of the trigger 63 is connected to the second inputs of the elements 65 and 66, and the inverse to the second inputs of the elements Both 64 and 67. The output of the AND element 66 is connected to the S-input of the trigger 62 and is the output 20 of the control unit 19. The output of the AND element 65 is connected to the R input of the trigger 63 and is the output 21 of the control unit 19. The output of the element AND 64 is connected to the first input of the element AND 68 and is the output 22 of the control unit 19. The output element And 67 is the output 23 of node 1 9 and is connected to the first input of the element And 69, the output of which is connected to the S input of the trigger 63. The input R of the trigger 62 is connected to the output of the element And 68, the second input of which is the output of the output permit The output signal of the output 23 of the node 19. The second input element And 69 is the input 26 of the device for controlling, and the C-inputs TpHi of the res 62 and 63 are combined and form the synchronization input of the node 19.

Logic unit 13 calculates the value of logical functions:

a, p / B „LA, (); L. V „, (); , LO.LA, (); g.U, 0 ,,, ().

where a- is the turn-on order signal

i-ro inverter; b - the order signal to turn on.

i-ro compensator-, d J - turn-off order signal

i-ro compensator g. - order off signal

i-ro inverter-, 20

pj, K, and -.- signals of identification of the state of thyristor converters:

at Pi 1, the i-th converter is in reserve 95 at K. 1 H-th converter — in the compensation mode, with the i-th converter is in inversion mode; ..- A, - signals at the first n outputs

scanning unit 24, A ,, - signals at the second n outputs

block 24, And - the signals on the third n outputs.

block 24.35

Logic unit 13 contains (FIG. 5) the group of elements ZI 70.1-70, p, the group of elements ZI 71.1-71.p, the group of elements ZI 72.1-72.P, the group of elements 4I 73.1-73.p and the element NO 74. The first the inputs of the elements. ZI 70.1-70.p and elements 4I 73.1-73.p are connected respectively to the first n outputs of scanning unit 24, the second n outputs of which are connected respectively to the first 5 inputs of the elements ZI 71.1-71.p, and the third n outputs from the first inputs of elements ZI 72.1-72. p. The second inputs of the ZI elements 70.1-70.p and elements 4I 73.1-73.p are connected respectively to the outputs for the signals /, - the Fiblock 14 mode memory, the outputs of which for the signals (K, -Cp) and (,) connected respectively to the second inputs of the elements ZI 71.1-71.p 55 and 72.1-72.p. The third inputs of the elements ZI 70. 1-70.p, 71.1-.71.P, 72.1-72.P and the elements 4I 73.1-73.P are

40

0

with

0

five .-

five

5 0 5

0

respectively, by enabling inputs of inverters, turning off compensators, turning off inverters and turning on compensators of unit 13, and are connected respectively to the outputs of comparison circuits 8-11, with the third inputs of ZI elements 70.1-70.p through element HE 74 connected to the fourth inputs of elements 4I 73.1- 73.p. The outputs of the ZI elements 70.1-70.P, 71.1-1.1p, 72.1-72.p and the elements 4I 73.1-73.P are the outputs of the logic unit 13, respectively, for the signals. n, -u; , d, Td, g, fg and, for turning on the inverters, turning off the compensators, turning off the inverters and turning on the compensators.

The mode memory block 14 (Fig. 6) contains two registers 75.1-75.p and 76.1-76.p on synchronized two-step RS-triggers and n two-input elements And 77.1-77.p. The S- and R-inputs of the trigger 75.1-75.p and 76.1-76.p form the recording inputs of block 14, while the S-inputs of the trigger 75.1-75.p and 76.1-76.p are connected to the outputs of the logic unit 13 for signals (n, fa) and (di-fd), and the R inputs of the triggers 75.1-75.p and 76.1-76.p are connected to the outputs of the logic unit 13 for signals (and ()), respectively. The direct outputs of the triggers 75.1-75. P are the outputs of block 14 for signals B, -B of the on-off control of the inverters and at the same time serve as the outputs of block 14, on which the signals of and are formed, and the identification of thyristor converters, operation Inverting mode. The inverted outputs of the flip-flops 76.1-76. form the outputs of block 14, which serve to issue signals C, -Cn on and off of compensators and at the same time are the outputs of block 14 of mode memory for the identification signals of the converters operating in the compensation mode. The inverse outputs of the triggers 75.1-75.P and the direct outputs of the triggers 76.1-76.p are connected to the inputs of the corresponding two-input elements And 77.1-77.p, the outputs of which serve for issuing identification signals of the transducers in reserve. The installed inputs S ,, R of the trigger 75.1-75.p and 76.1-76.p form the inputs 29 of the block 14 and for manual setting the operation mode

thyristor converters 32.1- 32. p.

On time diagrams, accept the following notation:

Ujs signal at the input of the generator 25;

  signal at direct trigger trigger output 63

 - signal at the direct trigger output 62j

Ujg is the signal at the output 20 of the control unit 19;

Uj is the signal at the output 21 of the control unit 19;

Ujj is the signal at the output 22 of the control unit 19;

  signal at output 23 of control unit 19

Ujg - the signal at the output of the element OR 28;

Uyg - the signal at the output of the generator 59;

and, Uj is the process of changing codes at the outputs of analog-to-digital converters 4 and 5;

Uy / j is the process of changing the code at the output of multiplier 52,

and the 53 code change process at the output of the adder 53;

S 5, the process of changing the d.d.

the output of the computing unit 6;

5 - code change process on

the output of the computing unit 7;

the signal at the first output of the distributor 58 j signal at the i-th output of the distributor 58 (1 1 -: - п); the output signal (n + i) of the distributor 58 ();

jn + 1 signal at the output (2n + i) of the distributor 58 () j By is the enable signal for the inverters (allowing the converter to be transferred from the reserve to the inversion mode) at the output of the comparison circuit 8; (

Oy is the enable signal for the inverters to turn off (allowing the converter to be transferred from the inverted mode to the reserve mode) at the output of the comparison circuit 9;

0 |, is the enable signal for switching off the compensators (allowing the translation of the converter from

25

A, A IH-

139437610

compensation mode in reserve)

at the output of the comparison circuit 10;

with k, the enable signal of switching-on compensators (the resolution of converting the converter from the reserve to the compensation mode) at the output of the circuit

10 11 comparisons;

(p | - signal at the output of the element 77.1 (signal of identification of the converter, which is in reserve);

15 direct output signal

trigger 75.1 (transducer identification signal operating in inversion mode);

20 signal at the inverse trigger output 76.1 (signal identification of the converter operating in the compensation mode) {

signal at the output of element 70.1 (order signal for switching on the 1st inverter) signal at the output of element 73.1 (signal for switching on the 1st compensator);

the signal at the output of the element 71.1 (order signal to switch off the 1st compensator) i

output signal 72.1 (order signal to turn off the 1st inverter) J signal at the output of the element 15 (resolution signal by summation by subtractor 46); signal at the output of the element And

16 (subtraction resolution by adder-subtractor 46);

signal at the input of the element And

17 (summing signal by adder-subtractor 51);

and. - signal at the output of the element And

18 (adder subtraction enable signal-subtractor 51);

44 process of changing the code at the output of the adder-reader 46

Ujj - the process of writing code in register 50;

thirty

35

40

45

50

55

CLi b, d. gi

and

15u

and

17

25

CLi b, d. 35

gi

and

15u

and

17

C

it

a code change process at the output of the subtractor 51;

Vg-f - the process of writing code in register 57; B, - signal at the direct output

trigger 75.1 (i-ro inverter on-off signal))

Cj is the signal at the inverse output of the trigger 76.1 (on-off signal of the i-ro compensator);

(9U); - the process of converting converter 32.1 from reserve to inversion mode; (), - - the process of converting converter 32.1 from inversion mode to reserve; (K P) j - the process of converting the converter 32.1 from the compensation mode to the reserve;

(RK); - the process of converting converter 32.1 from reserve to compensation mode. The work of the thyristor power complex is as follows.

It is known that the efficiency of a valve converter (as well as any electrical equipment) decreases with decreasing load. When using a group of thyristor converters connected to a common output network and having the property of changing their operation mode from inverter to compensatory and vice versa, it is possible in principle to ensure high efficiency of the power supply system with minimal power equipment costs. For this, it is necessary to maintain the ratios all the time.

TLR P + P; IR Min,

(12)

where m is the number of converters operating in the generator (inverter) mode; LR is the nominal power of one converter operating in the inversion mode; Р - current active power

loads;

P is the power margin to ensure reliability. Expressions (1) and (2) mean that the total power of the transducers.

ten

five

20

five

0

five

0

five

0

five

converted to invert mode, i.e. generation of active power should be minimal and at the same time sufficient to power consumers and create some reserve of PJ to ensure reliability. Therefore, only as many inverters as there are really needed to power the load at the moment should be switched on for parallel operation. The discretization step of regulation by active power is equal to LR at the same power of the converters. In this case, the deviation of the load power from the total power of the included inverters must be within

(tyR-R) 7 R. (3)

With (tdR-P) P, it is necessary to transfer an additional converter from the reserve or compensation mode to the inversion mode. If (tLR- -P) lr + P ,, then this means that one of the inverters must be turned off.

The change in the magnitude and nature of the load also leads to a change in consumer demand for reactive power. In this case, the reactive power of the switching capacitors is spent on covering the reactive power of the load and creating a lock angle / 3.

The balance of reactive powers in the current inverter is determined by the well-known expression

Q Q + Ptg / 5, (4)

where Q is the reactive power of the switching capacitors; Q - reactive load power; Р - load power is active; P - corner lock.

In the inverter with compensator, the expression (4) is written as

QC Q + Ptg / iK + Q, (5)

where Q is the reactive power applied by the compensator to stabilize the locking angle; f is the nominal latching angle corresponding to the rated power of the converter. The magnitude of the reactive power applied by the compensator is determined on the basis of (5) as

QK QC - Q - Р tg p „. (6)

13

Naturally, the compensator should be calculated as iToObi its nominal power Q, (H was sufficient to cover the maximum possible uncompensated load of the reactive power of the switching capacitors

139437614

From expressions (12) and (13) it can be seen, that the excess of the total nominal power K liQ of the included compensators over the uncompensated load by the value (tg / j) of the power of the switching capacitors must be within

ten

(4Q + Qjp).

From expressions (12) and (13) it follows Q + Q (Q + Ptg H) - (Qc-K4Q) Q. (14)

When (Q + P tg / iH) - (Qc + KdQ) 74Q + Qji is not a certain level (/ i). Therefore it is important that. It is necessary to disable one of the compensations Q Q- (Q + Ptg / 5H) M «H- (7)

Rectifier-inductive compensators of the type used in this object provide automatic stabilization of the locking angle to the setpoint when the load changes, the power supplied by the switched-on compensators does not exceed their nominal value. Since in this object the change in the total nominal power of the switched-on compensators K /) Q is carried out discretely with a step lQ it is necessary to maintain its value at the level

20

When (Q + P tgjTj) - () Qj, one of the transducers in reserve or invert mode should be transferred to the compensation mode.

The mode of operation of the i-ro converter is determined by the state of the pair of like-named triggers of registers 75 and 76. The inversion mode corresponds to the state U 5, i., 1, i.e. both triggers are in a single state. In this case, the control input of the phase-impulse control unit 34.1 is given a signal of the logical unit B | -1, and the control input of the phase-shifting node 42.1 is a signal of logical zero C.0, which cause unlocking of the regulator 33.1 and establish the phase shift of the control pulses of the bridge 37.1 corresponding to the inverter mode. The compensation mode corresponds to the state U 7j. , /one

K (Q + P);

mm

(8) (9)

K aQ

Expressions (8) and (9) mean that the total nominal power of the converters transferred to the mode. compensation should be minimal but at the same time sufficient to cover the excess reactive power of the switching capacitors, i.e. power, uncompensated load. Consequently, the parallel operation should include only as many compensators as are really needed to compensate for the excess reactive power of the switching capacitors.

Expressions (8) and (9) specify the range in which the total nominal power of the compensators should be maintained, taking into account the discrete step 4 Q

K / 5Q7Qc- (Q + P) + Qji; (ten)

, - (Q + Ptg / jH), (P)

where Q ,, - some power reserve included compensators

to ensure reliability. Based on (10) and (11) we get

(K / sQ-Qc) + (Q + Ptg / iH) Qrf -, 12) (KiQ-Q J + (Q + Ptg / bH). Q- -Qj - (3)

When (Q + P tg / iH) - (Qc + KdQ) 74Q + Qji, it is necessary to disable one of the compensated

When (Q + P tgjTj) - () Qj, one of the transducers in reserve or invert mode should be transferred to the compensation mode.

The mode of operation of the i-ro converter is determined by the state of the pair of like-named triggers of registers 75 and 76. The inversion mode corresponds to the state U 5, i., 1, i.e. both triggers are in a single state. In this case, the control input of the phase-impulse control unit 34.1 is given a signal of the logical unit B | -1, and the control input of the phase-shifting node 42.1 is a signal of logical zero C.0, which cause unlocking of the regulator 33.1 and establish the phase shift of the control pulses of the bridge 37.1 corresponding to the inverter mode. The compensation mode corresponds to the state U 7j. , /one

whether

74,

Those. both triggers are found

c in the zero state, while the control input 35.1 of the block 34.1 of the pulse control phase is supplied with a logical zero signal B.0, and the control input of the phase-shifting node 42.1 is a signal of the logical unit C 1, which leads to the locking of the regulator 33.1 and shifting the control pulses of the thyristor bridge 37.1 in the direction of advance (as compared to the inverter mode) by the angle Р PH where g} is the coefficient depending on the compensator circuit and equal to 1/2 for a three-phase bridge circuit. The reserve mode corresponds to state 1, i.e. trigger 75.1 is in the zero state, and trigger 76.1 is in the single state. At the same time, signal B.0 is present at control input 33.1 of block 34.1, and a signal is present at control input 43 i of phase-shifting node 42.1, which causes the regulator 33.1 to lock and to establish the phase shift of control pulses 37.1 corresponding to the inverter mode.

Thus, the inversion mode is characterized by the fact that the constant voltage regulator 33.1 is open and the thyristors of the bridge 37.1 are pulsed, causing the conversion of the constant voltage to an alternating frequency f. To transfer the converter to the reserve mode, the controller 33.1 is locked, which leads to the cessation of the transfer of active power to the converter load 32.1 Control pulses on the thyristors of the bridge 37.1 while continuing to transfer The converter to the compensation mode is carried out from the reserve mode by shifting the control thyristor pulses by the bridge 37.1 to the angle "in the direction of advance with respect to the control pulses applied to the thyristor bridges operating in the inverting mode or being in reserve .

Conversion of converter 32.1 from compensation mode to inversion mode is also performed through an intermediate reserve mode by shifting the bridge control pulses 37.1 in the opposite direction before phase matching with the control pulses of the inverters and subsequently unlocking the controller 33.1.

The control of the group of thyristor converters is carried out according to the algorithm presented in FIG. The procedure for putting the converters into operation is as follows.

After turning on the power supply of the device, to control the inputs 29 of the -14 mode memory, it is necessary to establish such states of the trigger 75.1-75.p and 76.1-76.p that automatically provide the required operation mode of each converter. At the same time, the number of converters intended for operation in the inverter mode, the number of converters to which the compensatory mode is assigned, and the number of backup converters are determined by the expected value and nature of the. In the particular case when the thyristor complex is turned on to idle one of the converters

d g 0 5

five

five

0

five

should be assigned to the inverter mode, and the rest set to the compensation mode. In the future, the control system will automatically convert the transducers to the mode determined by the load. At the same time, input 30 of the register 50 of the computing unit 6 records the code of the initial value of the total power of the SRRD converters intended for operation in the inverter mode, and input 31 of the register 57 of the computing unit 7 introduces the initial value of the power (Qj. Where Kj is the number compensators, scheduled to be included in the compensation mode.

The preparation for operation of the thyristor complex is completed by applying a signal Reset to the input 27 of the control unit leading the node 19 to the initial state. After that, the inputs of the regulators 33.1-33.1 are supplied with the voltage of the primary network of frequency f, leading to the appearance of the voltage of the output network of frequency f ,. Automatic control of the thyristor complex is initiated (Fig. 8) by applying a potential On signal. to input 26 of the control device. As a result, the RS flip-flop 63 switches to the unit state with the arrival of the next clock pulse to the C input from the clock generator 25 and at the output 20 of the control unit 19 the control signal UjQ is generated, which is fed to the control inputs of the analog-digital converters 4 and 5 and launches them (Fig.9-12). After time 1, the conversion code of the current value of the active power P of the load is fed to the second information input of the subtractor 47 and the first input of the multiplier 52, the output of which, after time 7, is the value of P tg / i. At the same time, the code of the current value of the reactive power Q of the load from the output of the analog-to-digital converter 5 is fed to the first input of the adder 53, the output of which forms the code (Q + P tg / i).

Register 50 stores the code for the current value of the total power of the included tdR inverters, and register 57 for the code for the current difference value (Q -ICAQ).

With the arrival of the second clock signal on the C inputs of the flip-flops 62 and 63, the flip-flop 62 switches to a single network and generates a signal at output 21, which goes to the enable inputs of the subtractor 47 and 54 and the receive inputs of registers 48 and 55, respectively. As a result, a function code is established at the output of register 48.

S, ga lR - P, (15)

and the output of register 55 is the function code

S (Q + P tg / 5,) - (). (sixteen)

The codes of the S and S values are fed to the first inputs of the comparison circuits 8-11, the outputs of which, according to the results of the comparison with a constant coefficient, produce the signals of the logical unit, respectively

, with S, (17)

, with S, 7 LR + Pji; (18)

, with S, (19)

, with S, Q. (20)

With the arrival of the third clock signal (Fig. 4 and 7) on the C inputs of the flip-flops 62 and 63, the flip-flop 62 switches to the zero state and a single signal is generated at the output 22 of the node 19 and enters the input-element And 61 and permits the clock signals to the C input of the distributor 58 from the clock generator 59. Further generation of the control signals by the node 19 is suspended (FIGS. 8-12), since the second input of the And 68 element has a logical zero signal blocking the switching of the trigger 62. With the onset of the clock signals at the C input of the distributor 58, he begins to generate impulses A, -A successively at his Sn outputs. Thereby, at the beginning, the informing inputs of the logic unit 13, to which the signals identifying the presence and the numbers of the frequency converters in reserve are received, are viewed. If, in this case, the signal Bj, 1, then upon detection of the informative input, at which the logical unit level p.1 is present, the output of the element 70.1. Produces a signal Q.1, which enters the S-input of the trigger 75.1 and puts it into the unit state niya

15

20

25

(Fig. 6, 9). The signal from the direct trigger output 75.1 arrives at the control input 35.1 of the phase-pulse control unit 34.1 and opens the constant voltage controller 33.1. As a result, the converter 32.1 is transferred from the reserve to the inversion mode (Fig. 8).

Q At the same time, the signal from the output of the element And 70.1 goes through the element OR 15 to the input of the resolution of the summation of the adder-subtractor 46, to the input of the element OR 49 of the computing unit 6, and also to the input of the element OR 28. As a result (Fig. 3, 9), the sum- The torch subtractor 46 generates a new, increased by aP, power value of the included tLR inverters m / JP + 4P and enters the register 50. The signal of the logical unit from the output of the PChI element 28 is inverted by the inverter 60 and blocks the input of the clock signals to the C input of the distributor. This stops the scan, i.e. stops viewing further transducer modes. At the same time, the logical unit signal from the output of the element OR 28 enters the input of the element And 68, allowing the reset to the zero state of trigger 62. With the arrival of the next clock signal to the C input of the trigger 62, it switches to the zero state, as a result of which 19, a single signal is generated which arrives at K (, - input of the distributor 58 and resets it to its original state.

A new cycle of control of the thyristor complex, which proceeds as described, begins. If this reveals that the signal is 0-1, then during the scanning process, an informative input will be found, containing the signal and.1 identifying the converter in the inversion mode. As a result, at the output of the element 72.1, the Wits signal, which goes to the R50 input of the trigger 75.1 and transfers it to the zero state (Fig. 6, 10). Signal В .0 from the direct output of the trigger 75.1 will go to the control input 35.1 of the phase-impulse control unit 55.1 and 34.1 and close the constant voltage regulator 33.1. As a result, the converter 32.1 will switch from the inversion process to the reserve (FIG. 10).

thirty

35

40

45

At the same time, a signal from the output of the element OR 16 will initiate the operation of subtracting 1plR t / 5P-DR in the adder-subtractor 46. As a result, in register 50 a new value of the total power of the operating inverters is fixed, and the signal from the output of the element 28 is reset. the control unit 19 and the scanning unit 24 in the described manner.

If the measurement of the current active P and reactive Q load power reveals the inequality

(Q + P tgp,) - (Qc-KjQ) -7 dQ + Q,

This produces a signal 0, 1 at the output of the comparison circuit 10, which is fed to the inputs of elements 71.1-71.p of logic unit 13. In this case, when scanning unit 24 polls the informing inputs of logic block 13, to which signals are received, a single signal is generated d, - 1 at the output of the element And 71.1, which is fed to the S input of the trigger 76.1 and translates it into a single state (Fig. 5, 11). The signal from the inverted trigger output 76.1 arrives at the control input 43.1 of the phase shifting node 42.1 and moves the control pulses of the bridge 37 .1 towards the lagging side by the Ed Unit, i.e. The converter converts 32.1 from compensation mode to reserve. At the same time, the signal produced at the output of the OR 18 signal corrects the value () stored in the register 57 of the computational block 7, reducing it by / iQ in the manner described. At the same time, the signal from the output of the element 1Sh 28 stops the further scanning of the inputs of the logic unit .13, and then the node 19 and the block 24 returns to the initial state.

Similarly, the situation of the EB Q,. ((FIG. 5, 12) is processed, resulting in the appearance of the signal at the output of the comparison circuit 11. In this case, the resolving potentials 1 are present only at the inputs of the AND 73.1-73.p. Therefore, when scanning A transducer in reserve () is detected and, at the output of element 73.1, it forms a signal that arrives at the R input of the trigger 76.1 and brings it to the zero state.

d

with

about 5 5

0

0

0

This leads to the fact that at the control input 43.1 of the phase-shifting unit 42.1 a signal C appears, -1, causing the control pulses of the bridge 37.1 to be shifted towards the front by an angle Co. As a result, frequency converter 32.1 is transferred from reserve to compensation mode. This transfer is only carried out if the signal B 0, i.e. the total nominal power of the included compensators satisfies the tyR-R ratio. Otherwise, the inverter 74 blocks the transfer of the thyristor converters from the reserve to the compensation mode and ensures the elimination of the deficit of the total nominal power of the inverters by transferring one of the converters detected in the process scan from the reserve to the W1 converting mode described by the image, and only in the next, operation cycle of the control unit 19, does the 1 st converter convert the but in compensation mode.

When changing the load, a situation may arise when both inequalities (17) and (19) are fulfilled simultaneously.

S S, Q + Qj.

This leads to the appearance of two signals and simultaneously. In this case, if at least one converter is in reserve, it is transferred to the inversion mode, since AND 70.1-70.p elements are first scanned, to which signals are received (, identifying backup converters. Thus, first eliminating This is the first inequality, and only in the next cycle of operation of node 19 will the second inequality be eliminated. If there is no converter in reserve, then it becomes necessary to switch one of the compensators into inversion mode. in two cycles of operation of the control unit 19. In the first cycle, after interrogation of the elements 70.1-70.p, the scanning of the elements 71.1-71.p. begins. The converter with a smaller number (O), which is transferred to the reserve in the manner described. In the second cycle of operation of the node 19, when scanning elements 70.1-70.n, this converter is again detected and is transferred to the inversion mode.

Thus, in this case, first the second inequality is eliminated and then the first.

The described operation logic of the control device assumes that the thyristor complex is correctly calculated, i.e. the total power of its converters is sufficient to satisfy the load in active and reactive power over the entire range of its change.

From the timing diagrams of FIGS. 8-12, it can be seen that the clock frequency of the generator 25 is determined by the ratios

-T 1 25 2

P )

  ,

(21)

(22)

where t n - max (pm, ssr, -ir, i kp) i Crm is the time of conversion of the converter from the reserve to the inverting mode j

 conversion time of the converter from inversion mode to reserve;

rk

- time of translation

bodies from reserve to compensation mode;

 - the time of transfer of the converter from the compensation mode to the reserve;

 this is the total switching time of the delay flips 62 and 63 on the logic elements of the control and analog-to-digital conversion unit 19:.

multiplication time in block 52; the summation time in the adder 53. The value Tlch is determined by the maximum

we derive from the values obtained from expressions m (21) and (22). On practice

1/2, the frequency of the generator 59 is determined only by the frequency properties of the element base. The generation period should not be less than the total switching time of the distributor llpcn and the delay g on the elements of logical 1 5

Who block 13 and elements And 61, OR 28, and also 15-17 or 18

 i

f5

  rap,

(23)

Q

-, five

20

25

thirty

35

40

45

SP

-

55

The output frequency of the thyristor complex does not depend on the frequencies of the generators 25 and 59, but is determined by the frequency of the generator 45. In practice

59 T-S The positive effect of using the proposed device is that it provides a significant reduction in the total installed power of the equipment of the reactive power compensation system equipment by promptly converting the converters From inversion mode to compensation mode and vice versa. The fact is that with a nominal load of all thyristor converters operating on a common network, a compensator of relatively small power is required to stabilize the angle of locking when the load decreases only to a certain value. As the load drops, the proposed device switches part of the inverters into compensation mode and provides compensation for the reactive power released by the switching capacitors. When the load increases, the control device provides for the return transfer of compensators to the inversion mode. Thus, there is no need to have separate compensators for each converter, as is the case in known frequency converter circuits.

In addition, the proposed device provides an increase in K1SH of the power supply system and resource savings of the aggregates, since for parallel operation it always includes as many inverters and compensators as they are really needed to power the load at the current time, i.e. loading of operating units is always provided, is close to the nominal value, and the remaining converters are transferred to the reserve.

Claims (7)

Claims 1. Device for controlling a group of n thyristor converters combined at the output, each 231 of which includes a series-connected DC voltage regulator with a phase-impulse control unit having a control input, an LC-flash drive, a thyristor bridge with a control pulse-shaping unit, a power supply reactor and a battery of switching capacitors at the output, and a diode connected to the output of the LC filter in a non-conductive direction with respect to the supply voltage of the thyristor bridge and a 30-shearing node connected to the input of the control pulse shaping unit and having a control input a synchronization input, containing a common master oscillator connected to the synchronization inputs of all n phase shifting nodes, is designed so that, in order to reduce the installed power of the power equipment and increase the energy characteristics of the power supply system consisting of n frequency converters connected To the common output network, an active P sensor and a reactive Q load power sensor are added, the first and second analog-to-digital converters, the inputs of which are connected respectively to you by the active and reactive power sensor strokes, the first and second computing units are a scanning unit, a logic unit, a constant coefficient unit, a mode storage unit, a control node, , Four comparison schemes, five OR elements and a clock generator, the output of the first analog-digital converter connected to the information input of the first computing unit and the first information input of the second computing unit, the output of the second analog-digital converter connected to the second information input of the second computing unit , the output of the first computing unit is connected to the first inputs of the first and second comparison codes, the output of the second computing unit is connected to the first input The third and fourth comparison circuits, the codes, the outputs of the first, second, third and fourth comparison circuits of the codes are connected respectively to the enable inputs of the inverters, the off switches of the inverters, the off switches of the compensators and the resolution 24 switching on compensators of a logic unit, the first computing unit implements the function - S shlR-R, where S is the code at the output of the computational blockades and - the number of currently switched on inverters аР - rated power inverTopai Р - current active power loads the second computing unit implements the function S5 (Q + P tgLn) - (Qc-K4Q), where Sj is the code at the output of the computing unit, Q is the current reactive power load-, p „is the angle of the thyristors being locked at the nominal load of the converters; QJ, is the reactive power of the switching capacitors; K is the number of compensators currently switched on; dQ is the nominal power of the compensator, the first comparison scheme implements the dependency Bh 1, if S, P, where Bj, is the signal of a logical unit enabling inverters; 40 50 55 Pd-margin for the total rated power of the included inverters, the second comparison scheme implements the dependency 0 " one, if s, 4P + P where Oj is the logical unit resolution signal to turn off the inverters, the third comparison circuit implements function 0.1 if S 4QH-Q, where oh - the signal of the logical uni1 resolution off compensators-, Q J, - margin for the total nominal power of the included compensators. 25 fourth comparison circuit implements the function In 1, if S, Q where Bc is the signal of the logical unit for enabling the compensators J the inputs of the input codes of constant coefficients AP of the first computing unit, tg 5 "and uQ of the second computing unit are connected to the corresponding outputs of the block of constant coefficients; the second inputs of the first, second, third and fourth comparison circuits are designed to enter codes of constant coefficients Pn, (P + P, Qjji, (/ iQ + Qjt), respectively, and are connected to the corresponding outputs of the block of constant coefficients, the outputs of the logic block by four n-bit buses, which serve to send signals of orders to change the mode of operation transducers are connected to the recording inputs of the mode memory block, while ten 139437626 The second output for the third control signal for the third control signal is connected to the start input of the scanning unit and the fourth output for the fourth control signal of the control node is connected to the input of the reset unit scan, Sn outputs of which are connected to the scanned inputs of the logic unit, the output of the clock generator is connected to the synchronization input of the control unit and the synchronization input The recordings of the memory block of the modes, the outputs of the first, second, third and fourth elements OR and Zn-y. The output of the scanning unit through the fifth fifth input element of the NL is connected with the input of the Stop of the scanning unit and the input of the resolution of generation of the fourth control signal of the node 25, with Reset and On inputs, used to drive the control unit. 20 the inverter turn-on orders bus through the first p-input element OR is connected to the inverter turn-on input of the first computing unit; the inverter shut-down orders bus through the second OR input element is connected to the inverter's turn-off input input of the first computing unit; - input element OR is connected to the input of the account of switching on the compensator of the second computing unit, the order bus for switching off the compensators through the fourth p-input element Ш connected to the input of the shutdown account of the compensator of the second computational block; the memory block of the operation modes of the thyristor converters are connected to the information inputs of the logic block by the three n-bit bus identifiers of the modes, the output outputs of the on / off control of the mode memory inverters are connected respectively to the control inputs blocks of phase-pulse control, and n outputs of the on-off control of the compensators - respectively with the control inputs of the phase-shifting nodes, the first output d for the first control signal control node connected to the start input of the analog-digital PPE thirty 35 55 initialization and start-up, logic block realizes the functions but. BM L A; , (); B ,, l vc / a; , (); d, K. / 0, LA ,,, (Vn); About „LA,„. , () j 0 five b- g; five 0 where a. - signal of the order to turn on the i-ro inverter; signal of the order to turn on the i-ro compensator; signal of the order to turn off the i-ro compensator; signal order to turn off the i-ro inverter} 9-, K ,, 11.- signals to identify the states of thyristor converters} when the i-th converter is in reserve-, with K; 1 i-th converter is in compensation mode; when i-th converter is in inverted mode; the signals at the outputs (l-i-n) of the scanner; i the signal at the outputs () of the scanning unit; A. 2/1394376  - output signals () scanner unit. 2. The device according to p. 1, about t l and m in h in m in m in with you are with you or 1 or 2 or 5 In particular, the first calculating block contains a combinational adder-subtractor, a combinational subtractor, the first register, a two-input element SH and a second two-stage register, the output of which is connected to the first information input of the subtractor and the first information input of the adder-subtractor, the second information input which is used to enter the code of the constant coefficient dP, and the output is connected to the input of the second register, the setup inputs of which are used to enter the code of the initial power value tpdyr including Inverters, and the reception enable input is connected to the output of the OR element, the output of the subtractor is connected to the input of the first register, the output of which serves as the output of the computing unit, the information input of which is the second information input of the subtractor, the permission input of which subtract is connected to the reception input of the first register and is the input of the calculation resolution of the function of the computing unit, the resolution input of the summation of the summator subtractor is connected to the first input of the OR element and is the input of the calculation incorporation of the computing unit of the inverter, metering entrance turning off the inverter which is coupled to the enable input of subtractor summato- ra-subtracter and a second input of the OR element. 3. Device pop, 1, characterized in that the second computing unit contains a combination adder-subtractor, a multiplication unit, a combination adder, a combination subtractor, a first register, a two-input element OR, and a second two-stage register, the output of which is connected to the first information input of the allocator and the first information input of the adder-output elements AND And the element NOT, the first the reader, the second information input of which is used to enter the code of the constant coefficient uQ, and the output is connected to the input of the second register, the input of which is used to enter the initial value (Q (, - KQ4Q), where K is the initial number of compensators switched on, and entrance is allowed28 0 five 0 0 five 0 five The reception NIN is connected to the output of the GDI element, the second information input of the subtractor is connected to the output of the adder, the first input of which is the second information input of the computing unit, and the second input is connected to the output of the multiplication unit, the first input of which is the first information input of the computing unit, and the second input is for a kind of constant coefficient, the input of the summation resolution of the adder-subtractor is connected to the first input of the OR element and is the input of the inclusion of the compensator the output block, the subtraction enable input of the totalizer-subtractor is connected to the second input of the 1SH element and is the counting input of the compensator of the computing unit; the output of the subtractor is connected to the input of the first register whose output serves as the output of the computational block; the first register and forms the input of the resolution for calculating the function of the computing unit. 4. The device according to claim 1, that is, that the scanning unit contains a pulse distributor to Sn outputs for signals, a clock generator, a FiE element and a three-input element And, whose input is connected to the synchronization input of the distributor, and the first input connected to a clock generator; the second input of the AND element is connected to the output of the NOT element, whose input is the Stop input. scan stop, d PD - distributor input and the third input of the AND element serve as the Reset and Start inputs of the scanning unit, respectively. " 5. The device according to claim 1, characterized in that the logical block contains three groups of n three-input elements And in each, the fourth group of n four-inputs of the elements And the first, second, third and fourth groups form the scanned inputs of the logical block, with the first inputs the elements of the first and fourth groups are connected respectively to the inputs () of the scanning unit, the yyhody (n + 1-t-2p) of which are connected to the first inputs of the elements of the second group, and the outputs (2n- -1f3n) to the first inputs of the elements of the third groups, the second inputs of elements And p The second, third, and fourth groups form the informative inputs of the logic unit, the second inputs of the elements of the first and fourth groups are connected respectively to the outputs of the memory unit, which serve to issue signals 7 - P to identify the thyristor converters that are in reserve, and the second inputs of the elements of the second and third groups are connected respectively to the inputs of the mode storage unit, which serve to output the signals and and, and. identifying thyristor converters in the compensation mode and the inversion mode, respectively, the third inputs of the AND elements of the first, second, third and fourth groups are respectively the enable inputs of the inverters, turn off the compensators, turn off the inverters and turn on the compensators of the logic unit and are connected respectively to the outputs, the fourth, second and third comparison circuits, the fourth inputs of the elements AND the fourth group are connected to the output of the element NOT whose input is connected to the third The inputs to the AND elements of the first group, the outputs of the AND elements of the first, second, third and fourth groups are the outputs of the logic block for the signals () (d,), (g, -rg) and (b.4-bn) orders, respectively turning on the inverters, turning off the compensators, turning off the inverters and turning on the compensators. 6. The device according to claim 1, wherein the memory block of modes contains n two-input elements I and two n-bit registers on two-stage RS-flip-flops, the R-n S-inputs of which are the recording inputs of the mode memory, and the S-inputs of the first register flip-flops are connected to the outputs of the logic block for the signals a. ,, inverter switch-on orders, R-inputs of the first register flip-flops are connected to the outputs of the logic block for signals g, fg orders to turn off the inverters, S-inputs of the second register flip-flops are connected to the outputs of the logic block for signals 0 five 0 five 0 five 0 five 0 five  orders to turn off compensators, R-inputs of the second register flip-flops are connected to the outputs of the logic block for signals to turn on compensators, direct outputs of the first-register flip-flops are outputs for signals B, hV of the control of the inverter of the memory module and at the same time serve as outputs identification signals of the operating inverters, the inverse outputs of the second register triggers are the outputs of the mode memory for the on / off control signals of the compensators and at the same time serve as outputs of identification signals of working compensators, direct outputs of triggers of the second register and inverse outputs of triggers of the first register are connected respectively to the first and second inputs of the corresponding AND elements, the outputs of which are outputs of identification signals of thyristor converters that are in reserve, the installation inputs Sj and R g flip-flops are mode memory block inputs intended for. manual setting of the operation mode of the thyristor converters, t 7. The device according to claim 1, characterized in that the control node contains six two-input And elements and two two-stage RS flip-flops, the Rp-inputs of which are combined and form the Reset input of the control device, the direct output of the first trigger is connected to the first inputs of the first and The second elements And, the inverse output of the first trigger is connected to the first inputs of the third and fourth elements And, the direct output of the second trigger is connected to the second inputs of the second and third elements And, the inverse output of the second trigger is connected to the second inputs ne The first and fourth elements And, the output of the third element And is connected to the S input of the first trigger and is the first output of the control unit; the output of the second element And is connected to the R input of the second trigger and is the second output of the control node; the output of the first element And is connected to the first input of the fifth element AND is the third output of the control node; the output of the fourth element AND is the fourth control output of the control unit and connected to the first input of the sixth element And, the output of which is connected to the S-input of the second trigger, the K-input of the first trigger connected to the output of the fifth element And, second ... g CSp9C nycK The main input of which is the input of the output of the fourth control signal of the control unit, and the second input of the sixth element I is the enable input of the control device. VS t Phage. Of zg Q ,. L ... nineteen Jl, ,, 5, / I I RT / j I g fffKlf f i t-a one VL # / L7 Erj y / y Sw ch BtffS ishomes jHifveHuu rnoAP, (Qe - euS) Pud B vue / tfffuff measurement, (ftffi M Q) Calculation: S / tlR-R 8bi fuC t nue 1 bg (Q PtjflH) - (Qc - Lv) Wichie / ieHue: Su, 0u OK, SM f. Interrogation of the state of prevalence. B ipaiomira with unwillingness npuxaja Si Ci nL 2. KoppenmtifloSxa with meoZhoZinosgpi: tyr; tyr tafi Of - (Of - to Ad) t uO 9 CSpoc (lacquer spray and 6 CKOHUpoSaweStnieroanae Г5П „п n гк гГрп rk and rQl " CSpec X Sx ioveHue .. g V P P P PP PP PP P ... P P P PLLPL i П П П П П П П П П П ПППППП Vis Gyu PL P In) GK Guch yy Gk : ei V, t Z 9i % % %  - No; - FIG. 9 % Z Jjc i (w Mr. Y-Y-t (Rig. W iff yy, 5gnnn pp p pp p p ppppp.ppp FIG.