SU1390803A1 - Device for separating direction of transmission in duplex communication systems - Google Patents

Abstract

The invention relates to data transmission. The purpose of the invention is to increase throughput. The device contains a matching unit 1, switch 2, DAC 3 and 11, ADC 4, form

Description

00

with

about

00

about

00

139

address tel (FA) 5, memory blocks 6, 10, generator, subtraction block 8, cyt-i- math 9. Blocks 12 and P memory, divider 14, trigger 15, subtraction block 16, counter 17, threshold block 18. The FA 5 has a memory block, a permanent storage block, an adder, and a threshold block. After connecting to the communication channel, a short-term forced reset of all nodes is performed. The working cycle begins, to-ry it is possible to divide into three simultaneously occurring processes: 1) constant formation and correction of estimates

samples of transmitted signals (blocks 6 and 10, block 8, adder 9 and FA 5), 2) storing the counts of transmitted signals and the sum of counts of transmitted and received signals received during the initial Formation of estimates of the transmitted signal counts (blocks 12 and 13 are involved, counter 17 and block 18) | 3) compensation of samples of transmitted signals in the received total signal (block 16, block 12, divider 14, the device is adaptive). 1 z.p, f-ly, 1 ill.

The invention relates to the field of data transmission and can be used in duplex communication systems.

The purpose of the invention is to increase throughput.

The drawing shows the structural-electrical circuit of the device.

The device contains an input matching unit, 1, switch 2, first digital-to-analog converter 3, analog-digital converter 4, address generator 5, first memory block | 6, generator 7, first subtraction block 8, adder 9, second memory block 10, a second digital-to-analog converter 11, a third memory block 12, a fourth memory block 13, a divider 14., a trigger 15, a second subtractor 16, a counter 17, and a threshold block 18, the address generator 5 comprising a memory block 19, a permanent storage unit 20, an adder 21 and a threshold block 22.

The device works as follows.

By connecting to the communication channel, a signal from the data terminal equipment is momentarily forced to zero all the nodes of the device. Thereafter, the operating cycle of the device begins. In this mode, the operation of the device can be divided into three simultaneously occurring processes.

five

0

five

0

five

The first process consists in the constant formation and adjustment of estimates of the transmitted signal samples. It is implemented using the first 6 and second 10 memory blocks, the first subtraction block 8, the adder 9, and the address maker 5.

The second process is to memorize the samples of the transmitted signals and the sum of the samples of the transmitted and received signals from the communication channel during the initial generation of estimates of the samples of the transmitted signal. It is implemented using the third 12 and fourth 13 memory blocks, the counter 17 and the threshold block 18.

The third process is to compensate for the samples of transmitted signals in the received total signal. Compensation of the transmitted signals is performed by subtracting from the samples of the sum of the transmitted and received signals from the corresponding memory cell of the third memory block 12 from the samples, evaluating the corresponding level of the transmitter signal taken from the output of the divider 14.

The essence of the first process, the process of forming an estimate of the transmitted signals, is as follows.

Let some information process n (t) to be transmitted to the input of the matching block 1 be received. The signal y comes from the communication channel y (c), which should be separated from the signal n (t). The signal n (t), having passed the input matching block 1, is sampled by level and in time. In addition, each level is mapped by the corresponding binary combination n (k / {t). The binary combinations nj (kit) are fed to the input BTOporO of the digital-to-analog converter 11, where the signal n (k4t) is converted into an output signal n (t). In the general case, due to the influence of the connected communication channel, the output signal n (t) is not equal to the input signal n (t), i.e. p (t) 7 p (t). The sum of the signals n (t) Hy (t) (where y (t) is the received signal) is fed to the input of analog-digital converter 4, in which it is sampled and converted into the signal x (kit) n (kAt) + y (kut) . After that, the signal x (kit) is fed to the second input of the first subtraction unit 8 and to the input of the first memory block 6. The first memory block 6 is partitioned, with the number of sections being equal to the number of binary combinations ni (kjt) representing the transmitted signal n (t),

Thus, if the input matching unit 1 is k-bit, then the number of possible combinations nj (kAt) at k 8 is 256 (2,256). Therefore, in this case, the first memory block 6 contains 256 sections.

At the same time, in each section of the first memory block 6, the value of the transmitted signal n (t) is recorded corresponding to the number of this section. For example, let at the first moment the signal n (t) be received at the input of the input matching unit 1, which becomes the input matching unit 1 into the combination n () 128 10 000 000 ,,. Here the subscripts denote the base of the number system. I.

 The signal (k, 4t) is transformed into n (t) in the second digital-to-analog converter 11, is added to the signal currently being received from the communication channel y (t,), turns into a signal X () n, jj () + y ( in the analog-digital converter 4, and recorded in the 128th section of the first memory block 6. Moreover, each section of the first memory block 6 has the length MT of the k-bit of the dyne cells, where K,

from Q l 5

0

0

averaged coefficient i-ro transmitted level. The value is calculated in advance, based on the required quality of forming the estimate of the transmitted signal samples by the formula (4), recorded in the permanent storage unit 20 before the start of the communication session. The address builder 5 generates the addresses in each section of the first memory block 6, starting with the first and ending M, thereby ensuring the operation of the first memory block 6 performed on random access memory with random access in the register memory mode.

Thus, if M appears at the output of the input matching unit 1 — once the binary combinations n, - (kt) are equal in magnitude, then the communication channel responses to these numeric combinations are fixed in the i-th section of the first memory block 6 to addresses, starting with the first and ending I.

The address builder 5 provides addressing, starting from a single up to M-. In each section of the first .6 memory. This is done as follows. Let a binary combination appear at the first moment at the output of the input matching unit G, equal to (t) 128 10 000 000 j. This binary combination indicates in memory block 19 a memory cell with the address equal to 128. Since the memory block 19 is reset at the first time moment, zero is output at the output of the last one at address 128. This zero in the adder 21 is added to the logical unit arriving at its second input. The summation result, equal to one, indicates in the first memory block 6 the first memory cell in the 128th section, from which the former contents (i.e., zero) are read first, and then the value x (k At) is written (k, At ) + y (k, At). The logical unit from the output of the adder 21 is then compared with the value that is output from the persistent storage unit 20 in the threshold unit 22. In the case that the contents of this (128th) memory cell of the storage memory 19 is less than the value of M, d derived from Since the persistent storage unit 20 then a logical zero appears at the output of the threshold unit 22. If the contents of the 128th memory cell of block 19

Pvtiti becomes equal to or exceeds the value, then a logical unit appears at the output of threshold unit 22 and memory unit 19 at address 128 is zeroed out. In addition, the result of the summation - the logical unit from the output of the adder 21 is then recorded in 128-10 cells of the memory block

19 is stored and stored until I show the memory cell. Since the first mono output of the matching unit 1 does not reappear binary

when the last digital clock was reset, then when the analog digital converter 4 arrived, the first counts of the total transmitted and received signals, an early (k, it) + y (), which passes through the first block 8. The summation result equal to n () + + y (k, it) is recorded in the 128th memory cell of the second memory block 10. After the second cycle of operation, the memory in the rum block 10 will be equal to: ri, j () + y, () +

numeric combination, equal to)

 10,000,0002

M2Y

If this digital combination appears again at the output of the input matching unit 1, then the previous contents (i.e., one) are output from the 128th memory cell of the memory unit 19, which is added to the unit in the adder 21 again. The summation result, equal to two, is again recorded at the 128-Nry address in the memory block 19, indicates the second cell in the 128th section of the first memory block 6 and compares it again with M, jg in the threshold block 22, etc. Let be . Then, after transmitting 62 times the value of K (kit), the output of the adder 21 appears in a number different 63 (62 + 1), which indicates again in the first memory block 6 - THI the 63rd memory cell in the 128th the sections from where zero is first read, and then the value p () + y is written (kgjAt). At the output of the threshold unit 22, a logical unit appears which wrapped the 128th memory cell of the memory unit 19. After transferring 63 times the value of n (), the process repeats, the first memory stack of the 128th section of the first memory block 6 of the first memory is read its contents, i.e. p, c () + y (), and

then the value n, j (kg.jA t) + + Oez (kg At), etc. is recorded.

Thus, the address generator 5, in combination with the first memory block 6, produces delay and storage of samples of transmitted and received signal samples. At the same time, the adder 9 together with the second memory unit 10 produces an accumulation of samples of transmitted and received signal samples. The operation of the second memory unit 10 is controlled by the trigger 15 in conjunction with the switch 2. The work cycle for calculating the estimates of the transmitted signals is divided into two intervals. At the first interval, trigger 15 finds

in the zero state, thereby the output of the input matching unit 1 is connected via the switch 2 to the address inputs of the second memory unit 10. When a binary number (for example, 128) appears, the output of the input matching unit 1 in the second memory block 10 is indicated by 128-.

memory cell. Since the first

five

0

thirty

45

when the last time was reset to zero, then, when the analog-digital converter 4 received, the first value of the total transmitted and received signals equal to (k, it) + y (), which passes through the first block 8. the summation, equal to n () + + y (k, it), is written into the 128th memory cell of the second memory block 10. After the second cycle of operation in the second block 10, the memory will be equal to: ri, j () + y, () +

+ n

42.6

(kg At)

UZ (), etc.

 After passing the times of the value of n, 2jj (kit) (b 3 in this case) we get:

eZS3

P (x) ,, 34k; it) 4, y () (1) I -t .b1

When transmitting random text, digital combinations (k 4t) at the output of input matching unit 1 appear randomly, independently of each other. Therefore, the samples 3 of the received signal y () will be randomly distributed in the first memory block 6. Thus, it can be considered that the samples () are characterized by independence both between themselves and between the samples of the transmitter signal n (). Therefore, the dispersion (power) of the second term in equation (1) is equal to:

 M, -. Pc, nf, (2)

where the dispersion of samples of the signal of the opposite side or the power of the signal coming from the communication channel PC, etc.

The power of the first term (1), which is a useful summation result, is:

RSOESGY.PRA M -nl (). (3)

From here you can find R, the ratio of the power of the useful summation result to the interference power, which is

due to the signal coming from the communication channel. The RJ value characterizes the quality of the generated estimate of the i-ro level of the transmitter signal:

p-2

.

. M. - (4)

RL

 i ASSOCIATIONS Send

RS.pr

-pr.

It can be seen from equation (4) that by choosing the appropriate summation number M, which is then fixed in the permanent storage unit 20, it is possible to ensure an arbitrarily high quality of formation of an estimate of the i-th level of the transmitter signal. Approximately, it can be assumed that for large values of M in the i-th section of the second memory block 10 numbers are stored that are M times the values of the i-th level of the transmitter signal observed at the input of the communication channel. By reducing the divider 14 by M times, we obtain the estimates for each 1st level of transmitter signals.

The second process - the process of accumulating and storing samples of transmitted signals to the sum of samples of transmitted and received signals is performed using the third 12 and fourth 13 memory blocks, the counter

17 and threshold block 18. At the first moment of time, the listed blocks are reset. To the inputs of the threshold block

18 state values are counted

N

pore

which

e to

Nnop 2 (

M

I)

(five)

the number of possible binary combinations at the output of the input matching unit 1J

Thus, as can be seen from the description of the second process of accumulation

N

matching unit 1 and samples of the transmitted and received second digital-to-analog converter 11. If the state of the counter 17 is less then the output of the threshold unit

signals for the period of calculation of the transmitted signal level ()

pore

18 is zero, otherwise a logical unit appears that 50 forcibly flushes counter 17. Thus, the division ratio of counter 17 is equal.

At the moment of turning on the counter 17 is reset, therefore in the third 12 and fourth 13 memory blocks, zero memory cells are indicated. In the fourth memory block 13, zero is first read.

The received signal samples are stored together with the transmitted samples in the third memory block 12. In the fourth memory block 13, the sequence of transmitted samples n (k, .dt) is memorized.

The third process, the transmitter sample compensation process in the received signal, is as follows. A trigger 15 and a switch are used to calculate the estimate of the transmitted signal.

ten

15

and then the first value of the transmitted signal n (k, t) is written, and in the third memory block 12, the zero is also read and the value of the sum signal from the output of the analog-digital converter 4 is recorded at the first time instant, which is equal to

X, (CL t) n, (k, 4t) + y, (k.ut). (6)

Similarly, when the next numeric combination, n () is generated by the input matching unit 1, the memory block 13 is recorded at the second address (ngCkjdt), and the third memory block 12 is written at the same address

)) +

y, (k.

dt) (7)

20

25

thirty

35

4Q

etc. After the counter 17 reaches the state Nf, (5p, a logical unit appears at the output of the threshold block 18, which forcibly wraps the counter 17 and sets the addresses in the third 12 and fourth 13 memory blocks to zero.

From the fourth block of 13 memory, the value is read, n (k, dt), and from the third memory block 12 is read the value)) + + Y (k, At), which is fed to the second input of the second subtractor 16. The value of n () from the fourth memory block 13 is then used to output the corresponding evaluation of the transmitted signal n (k-At), which is stored in the second memory block 10. Thereafter, the value n (kAt) is recorded at the zero address in the fourth memory block 13, and the value in the third memory block 12 is written.

 wnop (it) + y / nopOcAt).

Thus, as can be seen from the description of the second process of accumulation

counts of transmitted and received

counts of transmitted and received

signals for the period of calculation of the transmitted signal level ()

counts of transmitted and received

The received signal samples are stored together with the transmitted samples in the third memory block 12. In the fourth memory block 13, the sequence of transmitted samples n (k, .dt) is memorized.

The third process, the transmitter sample compensation process in the received signal, is as follows. Trigger 15 and switch 2 are used to calculate the estimated signal to be transmitted. These nodes, together with the divider 14, the second subtractor 16 and the first digital-to-analog converter 3, compensate for the counts of the transmitted signals in the received signal. Indeed, when calculating the estimate of the transmitted signal, trigger 15 is in the zero state and connects switch 2 so that the output of the input matching unit 1 is connected to the address inputs of the second memory block 10. When compensating for the readings of the own transmitter in the received signal, the trigger 15 by the next clock pulse coming from the generator 7, goes into one state. Thereby, the output of the fourth memory block 13 is connected via switch 2 to the address inputs of the second memory block 10. The digital combination from the output of the fourth memory block 13, corresponding to the transmitted count n (), indicates the address in the second memory block 10, in which the estimate of the transmitted signal is calculated for this digital combination. This estimate is read from the second memory block 10 and goes to divider 14. At the same time, the digital combination n (k, At) from the output of the fourth memory block 13 also enters the divider 14. This digital combination determines the division factor of the divider 14. These division factors are calculated by the formula (4), therefore, depending on the level of the transmitted signal n-Ck-At) at a fixed amount of interference, divider 14 has different division factors.

The output signal of the divider 14 is equal to

A1G

nj (k, -At). (k, -At.)

m, - Z yf (k-At)

i

(eight)

Further, the obtained estimate of the transmitted signal is subtracted in the second subtraction unit 16 from the total received and transmitted signals of the 1 count of the transmitted signal. This, from the sum of the transmitted and received signals, compensates the transmitted signal, thereby separating the transmission path from the reception path.

The device is adaptive.

five

0

five

0

five

0

five

0

Indeed, when changing the parameters of the communication channel, the level of the transmitted signal at the input of the communication channel also changes. However, through the Mj clock cycles of the device, the transmitter signal counts are recorded in the first memory block 6. The estimate of the transmitted signal, which is stored in the second memory block 10, is calculated, and the device adjusts to the changed parameters.

Claims (2)

Invention Formula 1, A device for dividing transmission directions in duplex communication systems comprising a first digital-to-analog converter, an address generator, a second digital-to-analog converter, an analog-to-digital converter, a first memory block, a first subtraction block, an adder and a second memory block, sequentially connected a generator connected in series, an input matching unit and a switch, the output of which is connected to the second input of the second memory block, the third input of which, as well as the second input of the first memory block, in The analog input of the analogue-digital converter and the first input of the address generator are connected to the generator output, the output of the analog-digital converter is sub- | Key to the second input of the first subtraction unit, the output of the second memory unit is connected to the second input of the adder, the input of the second digital-analog converter is connected with the third input of the first memory block, which is based on the fact that, in order to increase the throughput, a trigger, a threshold block, a third memory block, a serially connected counter, a fourth block the memory, the divider and the second subtraction unit, the second input and output of which are connected respectively to the output of the third memory block and the input of the first digital-to-analog converter, the generator output is connected to the first input of the third block, the memory, the second input of the fourth memory block, the trigger input and the first input of the counter, the output of which is connected to the second input of the third memory block and the input of the threshold unit, the output of which is connected to the second input 11139080312 counter, the output of the input 2. The device according to claim 1, about the t of the block is connected to the input of the second one by the fact that a digital-to-analog converter is formed, the second address contains a sequential input of the address generator and v-connected permanent third memory of the fourth block pa-block , threshold block, memory block and memory, trigger output is connected to an accumulator, the second input of which is the second input of the switch, third is the input of a logical unit, and the input of which is connected to the output of the even-output output connected to the second inputs of the true memory block, output fo The front-end unit and the memory unit, the address tracker is connected to the fourth input of which is connected to the input of that input of the first memory unit, your permanent storage unit and the analog-to-digital converter input the second input of the imaging device to the third input of the third address, the first input and output of the memory box, and the output of the second block 15th are respectively the memory connected to the second input, the second input of the memory block and the output of the memory adder.