SU1387148A1 - Method of converting d.c. voltage to 3-phase a.c. voltage - Google Patents

Abstract

The invention relates to electrical engineering and can be used in converters of direct voltage to three-phase AC with galvanically uncoupled loads, mainly for electric AC drives. The formation of an alternating voltage in each phase of the load is carried out by the method of pulse-width modulation by connecting the load to a source of direct voltage in a direct or reverse polarity or load locking. To eliminate the zero-phase output voltage in a three-phase system, the voltage of the two leading phases is formed independently, and in the third slave, depending on the state of the leading phases, all three phases are used alternately to provide phase symmetry. 1 hp f-ly, 4 ill. with

Description

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The invention relates to electrical engineering and can be used in three-phase output converters with electrically unconnected load phases (voltage inverters, direct frequency converters with artificial switching using bridge circuits per phase), the output voltage of which is formed by the methods WIRE or .SIM , and intended primarily for the purpose of the frequency electric drive or autonomous power supply.

The aim of the invention is to improve the quality of the output voltage by obtaining a balanced three-phase voltage in frequency converters with electrically unconnected load phases.

FIG. Figure 1 shows one of the possible structural diagrams of a device that implements the proposed method as applied to the control of a three-phase voltage inverter; in fig. 2 is a block diagram of the channel of the device logic block; in fig. 3 is a table of the cyclical control of the inverter valves; in fig. 4 shows timing diagrams explaining the method.

The device (Fig. 1) contains a three-phase voltage inverter, consisting of three identical single-phase bridge circuits 1-3, each of which in turn contains four fully controlled valves 4-7 and four reverse diodes 8-11, a three-phase load 12 with electrically unconnected phases A, B, C (13-15), control system 16. The control system (SU) 16 includes a master oscillator 17 pulses (DG), whose input is the first input of the control system determining the frequency of the output voltage of the converter, a seven-bit binary frequency divider 18 (DF) connected to the output of the master oscillator, reference voltage generator 19 (GON) and modulating voltage generator (HMN) 20 (controlled by the second input of the control system specifying the value of the output voltage of the converter), connected respectively to the five younger and four oldest frequency divider 18, multiplicity switch 21 (PC) connected to the ring with the reference voltage generator 19, sensor 22 cycles (DC) connected to the modulating voltage generator 20, trigger 23 forming selector pulses (TSI) connected to the input the GON reference voltage generator, comparators 24 and 25, connected by inputs to the outputs of GONE and GMN generators, an EXCLUSIVE logic circuit 26, connected to the comparators outputs, a distributor 27 pulses (CID), associated with the outputs of the comparators, a logic circuit EXCLUSIVE IL And, trigger the selector

pulses, the three vector outputs of the pulse distributor are connected to the valves of each phase of the inverter power circuit. Dispenser 27 pulses each

of the three channels contains (Fig. 2) eight AND 28-35 logic circuits connected to the inputs of the logic circuit OR 36, the output of which is connected to the gates 4 and 5, respectively, of the power circuit, three logic circuits NOT 37-39 connected between the distributor inputs and logic circuits AND 31-33, the logic circuit is NOT 40 and OR 41, the inputs of the logic circuit OR 41 are connected to two outputs of the frequency divider 18 directly, and to the other two - through logic circuits And 42 and 43, the second the inputs of which are connected with the outputs of the trigger of the TSI selector pulses, the outputs of the circuit OR directly and via inv PTOP NO 44 associated respectively with the rectifiers 7 and 6 of the power circuit.

0 The generators of the reference 19 and modulating 20 voltages generate, respectively, the triangular and sinusoidal voltages, approximated by right-angle functions obtained

5 by summing over impulses with corresponding weights. The multiplicity switch 21 contains a measuring device at the input, a pulse selector for duration associated with the multiplication and reduction multiples (triggers), which are connected to the reference voltage switching unit (key circuits) whose outputs are connected to the second inputs of the magnification blocks and decreasing the multiplicity and the reference voltage generator. Comparators 24 and 25

5 are comparison circuits on operational amplifiers. The sensor 22 cycles performed on the shift register on. The distributor 27 pulses contains only standard logic cells of the type AND, OR, NOT.

The method of converting a constant voltage into a three-phase voltage using a three-phase voltage inverter in the sinusoidal pulse-width modulation mode is carried out as follows.

The period of the output voltage of the converter is divided into two intervals at the intersection points of the three-phase sinusoidal voltage (Fig. 4a). If we set the formula of the modulating voltage on only one sci-fi part of the period in all three phases (curves X, Y, Z in the first interval, Fig. 4a), then the voltage in the remaining sections can be obtained by cyclic permutation through one sci curves

5 Z, Y, X.

In fact, the curve of the modulating voltage of a sinusoidal form is not synthesized in an explicit form from these sections, but directly uses two modulating voltages of the form Z and (-Y) (Fig. 46). A step-by-step approximation of these curves makes it easy to generate by summing pulses of equal duration.

The triangular reference voltage is also obtained by its right angle-step approximation, and its frequency is a multiple of the frequency of the modulating voltage intervals, which is ensured by starting the modulating voltage reference generator (Fig. 1) from one master oscillator 17 through frequency divider 18 s different division factors for these two generators. At the same time, the frequency division factor for starting the modulating voltage generator remains constant, and the frequency division factor for starting the reference voltage generator changes, because of the three constantly available reference voltages of the GON generator, obtained when they start from 1-3, 2–4, 3–5 younger bits of the frequency divider (with eight speed steps per saw), only one is used at a time. For this, the duration of the reference voltage period is compared in the measuring device of a switch 21 of multiplicity with two pulses of the reference length that differ by a factor of two. An increase (decrease) in the reference voltage compared to the maximum (minimum) reference duration triggers an increase (decrease) multiplicity unit, which, through the reference voltage switching unit, connects to the GON output that reference voltage from the existing ones, which has a smaller (larger) a) period duration, i.e. greater (smaller) multiplicity.

At the intervals of excess of the modulating voltage over the reference one, two sequences of rectangular pulses Z and y are produced at the outputs of the comparators 24 and 25 (Fig. 4c, d), after processing by the logic circuit EXCLUSIVE OR 26, a third sequence of pulses is obtained (z-y) 4d).

The distribution of the pulses of the three sequences over the valves is carried out in accordance with the logic of the formation of the three-phase sinusoidal voltages shown in the table (Fig. 3). Here, the indices A, B, C of valve numbers 4 and 5 mean that these valves belong to the corresponding phases. To control this distribution, cyclic pulses are generated in six channels of interval 22 in an interval of intervals shifted in each channel by an interval relative to adjacent channels and having a repetition period of the output voltage (Fig. 4c, first-cycle cyclo-pulse ).

Also, for the purpose of controlling the distribution, selector pulses are generated in block 23, corresponding to the intervals of excess modulating voltage Y over modulating voltage Z (Fig. 4g), which corresponds to the first half of the cyclic pulses. When the modulating voltage is approximated by eight steps per cycle, the trigger trigger pulse 23

 It is taken from the divider 18 frequency two binary bits to the right, i.e. from the sixth bit D4 than the trigger pulses for the generator 20 of modulating voltage.

The distribution of pulses over the inverter valves will consider for the algorithm of asymmetric metric bridge control, when modulated pulse sequences (Fig. 4h and, respectively) are fed to valves 4 and 5 (Fig. 1) of one arm of the bridge INA and respectively to valves 6 and 7 of the other arm bridge - unmodulated pulses

 (Fig. 4k, l, respectively).

In the first cycle, the voltage in phase A of the load must be formed in accordance with the modulating voltage.

5, therefore, control pulses from the sequence z (Fig. 4c) are passed to the gate 4, this is provided by the AND circuit 28 and the OR circuit 36 of the pulse distributor 27 (Fig. 3). Then the voltage on the load 12 of the phase 3A will have the form of positive pulses (Fig. 4m) at the moments of simultaneous switching on of the valves 4 and 8. At the same time, the valve 5 is supplied with control pulses (Fig. 4) and the corresponding inversions (using the scheme NOT 40) control pulses of the valve 4, which, when the valve 8 is turned on, ensures the formation of zero pauses in the output voltage. In the second cycle, the voltage in phase A of the load must be generated in accordance with the modulating voltage Y, therefore control impulses from the sequence y pass through valve 4 (Figure 4d). This is provided by circuit 29 and circuit 36 of pulse distributor 27 (fig. 3). On the valve 5 are the inverse pulses of the valve 4.

In the third cycle, the voltage in phase A of the load must be formed in accordance with the modulating voltage Y, but an independent pulse sequence corresponding to this voltage is not generated. Instead, formed by the operation EXCLUSIVE OR sequence of pulses (z-y), the pulses of which pass to valve 4 during the first half of the third cycle through the circuit AND 30 and the circuit OR 36. In the second half of the third cycle to the gate

 4, control pulses from the inversion are provided by the NOT circuit 37 of this sequence, T.e.Vz-y through the circuit AND 31 and the circuit OR 36.

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In this case, in the case of a load in the form of an asynchronous motor, in the motor current there will be no zero-sequence components, which provides improved utilization of the inverter and the motor.

Claims (2)

Claims 1. A method of converting a constant In a similar way, the control pulses on gates 4 and 5 and in the remaining (IV-VI) cycles are distributed in accordance with the table (Fig. 3), and the corresponding gates 4 and 5 of the other two phases of INV, ANS, are controlled in the same way. - the formation of the other two phases (fig. 4n, o) of the three-phase system of output voltages along with the voltage of phase a (fig. 4m). Thus, on four cycles of 10 voltages to a three-phase alternating voltage for each phase, non-electrically powered non-voltage is formed load-dependently on the other phases (for phase A, the fuzz is made up of cycles I, II, IV, V), and in two cycles - the load voltage of each phase is three-dependent on the voltages of the other two phases, by connecting the load to (for phase A, these are cycles III and VI). In each source of constant voltage in my The cycle always has two phases of the inverter control - 15 "reverse fields and short circuits are independent of the other phases, and a third of the load, distinguished by the fact that, in order to improve the quality of the output voltage by obtaining a balanced three-phase voltage, the voltage two leading phases are formed according to a predetermined law, and the voltage of the third driven phase is formed depending on the voltage of the driving phases, namely, with different voltage or zero voltage, the leading phases in the driven phase are formed by zero-direction (and accordingly mpulsov howling voltage 25, at zero voltage to the load voltage phases) in two not-in a leading phase and nonzero the phase is controlled dependently (on the sequence (z-y) on the state of two independent phases so as to ensure equality UA + UB + UC O those. to obtain a balanced three-phase voltage, moreover, symmetrical in phases. Practically, this is ensured by the fact that in the presence of timing pulses depending on the phases operating in this cycle, the timing control pulses are absent in the third (dependent) phase (which means that the voltage of the third phase is zero). And in the absence of voltage in one of the independent phases, the voltage in the dependent phase is set (using the z-y chroning sequence) with the opposite voltage in the second independent phase. thirty the voltage in the other leading phase, the voltage of the driven phase is formed opposite to the polarity of the leading phase, 2. A method according to claim 1, characterized in that, in order to obtain a symmetrical three-phase voltage, each of the load phases is alternately used as a slave phase alternately through a single part of the output voltage period. In this case, in the case of a load in the form of an asynchronous motor, in the motor current there will be no zero-sequence components, which provides improved utilization of the inverter and the motor. Claims 1. A method of converting a constant voltage to three-phase variable for ani electrically unrelated loads the voltage in the other leading phase, the voltage of the driven phase is formed opposite to the polarity of the leading phase, 2. A method according to claim 1, characterized in that, in order to obtain a symmetrical three-phase voltage, each of the load phases is alternately used as a slave phase alternately through a single part of the output voltage period. Fi.2 I Zh F si d si and U LJIIIILJ and F 1g.