SU1386993A1 - Multichannel priority device - Google Patents

Abstract

The invention relates to computer technology and can be used in local computer networks of distributed control systems, for example, technological processes based on microcomputers such as SM computers and Electronics-60, NTs-80. The aim of the invention is to increase the speed of the device by reducing the time to connect subscribers to the common highway. The device contains in each channel, an interrupt node, a start node, a counter, a transceiver, a shift register, a pause indicator, a pulse distributor, a comparison circuit. The invention allows priority connection of subscribers to a common trunk using an algorithm of accelerated decentralized code control. The use of the latter, which has the minimum among the known code control algorithms with the sequential transmission of code overhead, allows to achieve the purpose of the invention. 4 hp f-ly, 5 ill. I w

Description

CAD 00 05

;about

CD

GO

The invention relates to computing, in particular, to priority exchange devices, and can be used in computer-to-machine communication systems controlling access to a common resource (e.g., a common highway).

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of a multichannel priority device; in fig. 2 - block diagram of the pause indicator; in fig. 3 is a block diagram of the receiver call node; in fig. 4 is a flow chart of the launch site; in fig. 5 is a block diagram of an interrupt node.

15

20

The priority device contains in each channel 1 transceiver 2, indicator 3 pauses, distributor 4 pulses, shift register 5, comparison circuit b, receiver call node 7, start node 8 interrupt node 9, counter 10., AND 11-13 elements, OR elements 14 and 15, AND-NOT element 16, device request input 17, device start input 18, device input / output 19, trunk 20, information output 21 of the device, output 22 of the device interrupt.

The pause indicator 3 (Fig. 2) contains a single vibrator 23, a pulse generator 24, a counter 25 of the comparison circuits 26-28, a delay element 29, a NOT element 30, and OR elements NOT 31 and 32.

The receiver call node (Fig. 3) contains a HE element 33, a trigger 34, a HE element 35, a trigger 36, a pulse generator 37, a trigger 38, a one-shot 39.

The startup node 8 (FIG. 4) contains an AND-HE 40 circuit, a counter 41, a comparison circuit 42.

Interrupt node 9 (FIG. 5) contains a NOT 43 element, an OR-NOT 44 element, a HE 45 element, AND elements 46 and 47, a delay element 48, a trigger 49, an OR element 50 and a trigger 51.

The device works as follows.

After supplying the supply voltage to the device, any computer (subscriber) initiates the computer computer system start, supplying zero potential to the device 17, which through the element 12 transceiver 2 is connected to the trunk 20 and through the circuit 11 it sets it in the mode “Transmission. COMPUTER. Displays a start initiation command to trunk 20.

If the priority code bit is “O, the latter translates the transceiver 2 into the“ Receive. The information from highway 20 is fed to the second input of the comparison circuit 6, to the first input of which, from the output of register 5, the level "O" is applied.

After the distributor 4 generates the number of pulses, the corresponding priority code priority in the register 5. The operation of the distributor 4 is suspended. Counter 10 records the code corresponding to the number of the subscriber in the queue for connection to the highway, while its output is level 1, and the indicator 3 pauses from the second output of distributor 4 receives the potential O that resolves its operation. In indicator 3, the counting pulses from the generator 24 output through the OR-NOT 32 element are sent to the counting input of counter 25. When a pulse 25 arrives at the input of the counter 25, multiples of the propagation time of signals through the highway, signals appear at the outputs of the comparison circuits 26-28.

The pause in the highway is estimated to be four times longer, the receipt of the signal propagation time along highway 20. After this time has elapsed, the pulse from the output of circuit 27 goes to the subtracting input of counter 0. At the same time, the recorded code is reduced by one. Suppose that the counter 10 is recorded ". Then, at the output of the counter 10, a logical level "O" arrives at interrupt node 9 at the first input of the element OR-NO 44, at the second input of which there is a level "O, from the output of the trigger 49 and further to the third input of the element 46. At In the input element I 46, the level is "1, and at the first input is the last bit of the priority code.

If the last bit of the priority code is equal to one, then the positive voltage drop from the output of the element is 46 through 5

40

computing system. By this in command, the delay element 48 and the OR element 50 in the counter 41 of the start-up node 8 are written to the single input of the trigger 49, the binary code corresponding to the code written in the circuit 42. At the same time, the output of the node 8 is “Oh, the connecting transceiver 2 to the trunk 20 and allowing the work of the distribution of the highway 55, the subscriber sets to connector 4. The first pulse from the output of the distribution input of the trigger 51 is the level“ 1. The unit 4 is fed to the input of the shift register 5, at the output of which the switch to the state “1, prohibits further generation of interrupt signals, and to the clock of the trigger code 51.” If necessary, connect to

In this case, at the second output of the interrupt circuit 9, an interrupt signal pro5 appears.

0

five

The first bit of the subscriber priority code (priority codes are entered in query mode 5). If the priority code bit is equal to "1, it is transmitted to trunk 20. In this case, the signal of level" 1 IS-NOT 16 elements, at the second outputs of which potential is located "1, is fed to the input of transceiver 2, switching it to the" Transfer "mode and through the circuit OR 14 and AND 13 and transceiver 2, the signal enters the trunk 20.

If the priority code bit is “O, the latter translates the transceiver 2 into the“ Receive. The information from highway 20 is fed to the second input of the comparison circuit 6, to the first input of which, from the output of register 5, the level "O" is applied.

After the distributor 4 generates the number of pulses, the corresponding priority code priority in the register 5. The operation of the distributor 4 is suspended. The counter 10 records the code corresponding to the subscriber's number in the queue for connecting to the highway, while its output is level 1, and the indicator 3 pauses from the second output of the distributor 4 receives the potential O which allows it to work. In indicator 3, the counting pulses from the generator 24 output through the OR-NOT 32 element are sent to the counting input of counter 25. When a pulse 25 arrives at the input of the counter 25, multiples of the propagation time of signals through the highway, signals appear at the outputs of the comparison circuits 26-28.

The pause in the highway is estimated to be four times longer, the receipt of the signal propagation time along highway 20. After this time has elapsed, the pulse from the output of circuit 27 goes to the subtracting input of counter 0. At the same time, the recorded code is reduced by one. Suppose that the counter 10 is recorded ". Then, at the output of the counter 10, a logical level "O" arrives at interrupt node 9 at the first input of the element OR-NO 44, at the second input of which there is a level "O, from the output of the trigger 49 and further to the third input of the element 46. At In the input element I 46, the level is "1, and at the first input is the last bit of the priority code.

If the last bit of the priority code is equal to one, then the positive voltage drop from the output of the element is 46 through 5

0

 the delay element 48 and the OR 50 element are fed to the single input of the trigger 49, the subscriber sets the bus at the information input of the trigger 51 to the level “1.

its transfer to the state "1, prohibiting the further generation of interrupt signals, and to the clock code of the trigger 51. In case of need to connect to

  the delay element 48 and the OR 50 element are fed to the single input of the trigger 49, the subscriber sets the bus at the information input of the trigger 51 to the level “1.

In this case, a program interrupt signal appears at the second output of interrupt circuit 9. The subscriber establishes at the device input 17 a zero signal “Transmission and starts a communication session.

If the last bit of the priority code is equal to "O", then the program interrupt signal is not generated when the counter 10 is zeroed, since the subscriber can exit the line, the last bit of which priority code is equal to "1. Therefore, if there is such a subscriber, then the first start bit of the transmitted frame of information enters through the OR-NOT 31 element to the input of the one-shot 23. A single-vibration produces a positive pulse, the leading front of which zeroes the counter 25 and prohibits the passage of the counting pulses from the output of the generator 24 to the counting input of the counter 25. Therefore, an interrupt signal of the subscriber’s work program is not generated. After the end of the communication session, the signal from the output of the circuit 26 goes to the second input of the interrupt unit 9 and through the elements AND 47 and OR 50 to the inputs of the flip-flops 49 and 51, setting them to the state "1, thereby forming a program interrupt signal and blocking further formation interrupt signals. The subscriber, having received the interrupt signal, sends to the input 17 of the device a zero Transmission signal and starts a communication session. If the subscriber has the highest priority code, he completely transmits it to the trunk, and the pulse counter 10 remains in the initial state "O." In this case, the signal from the second output of the distributor 4, which arrives at the third input of the interrupt unit 9, generates an interrupt signal for the operation of the subscriber program. After servicing all requests, the pause start signal from the first output of the 3 pause indicator in none of the channels causes an interruption.

After some time has passed, the output of the circuit 28 of the indicator 3 appears, which makes the initial installation of all the nodes and through the delay element 29 enters the second input of the distributor 4, performs a restart. In this case, the order of subscribers exit to the mono channel is repeated.

The output of the information receiver is as follows. After determining the sequence of the subscriber, at the input of the bus sample of transceiver 2, the potential "1" is determined, which determines the "Receive. Information from the trunk through transceiver 2, element OR 15, at the second input of which potential ОO is located, from the second output of distributor 4 goes to the second input of call node 7. A single vibrator 39 of node 7, when the last bit of the field of the information frame flag arrives, generates a pulse that sets the trigger 38 to the “O” state, thereby allowing the generator 37 clock pulses to operate. When entering the clock input register 34 clock pulses in

the last is the address of the called party. When the given and recorded in the circuit 35 coincides, the potential "O from the output of the circuit 35 sets the trigger 36 to the state" 1, thereby generating the subscriber's program interruption request signal. At the end of the information frame, the falling edge of the signal coming from the fourth output of the indicator 3 is set to the initial state of the register 34, the triggers 36 and 38, and the generator 37.

Claims (4)

Invention Formula five 0 five five 1. A multichannel priority device containing a pulse distributor in each channel, a transceiver, a comparison circuit, a shift register, a pause indicator, a receiver call node, the transceiver information input, the first pause indicator input and the first input of the comparison circuit are connected to the common highway, comparison is connected to the output of the shift register, the clock input of which is connected to the first output of the pulse distributor, characterized in that, in order to increase the speed of the device, each channel entered start node, interrupt node, counter, three AND elements, two OR elements, AND-NOT element, the first input of which is connected to the output of the comparison circuit and to the counter control input of the counter, summing and reading input of which is connected respectively with the first outputs of the pulse distributor and the pause indicator, the output of which is connected to the first inputs of the interrupt node and the first OR element, the second input of which is connected to the first output of the interrupt node, the second input of the AND element is not connected to the first input of the OR element, The output of the element AND is NOT connected to the first input of the first element I, the second input of which is connected to the corresponding request input of the device and to the first input of the second element I, the output of the first element I is connected to the transmission control input of the transceiver whose input control input is connected to the output of the second element And, the control input connection to the transceiver trunk is connected to the output of the third element AND, the first input of which is the device start input, the second input of the third element AND is connected to the output the house of the first element OR, the second output of the pause indicator is connected to the stop input of the pulse distributor, the third output of the pause indicator is connected to the second input of the interrupt node, the fourth output of the pause indicator is connected to the first input of the receiver's call node, the output of the trigger node is connected to the start of the pulse distributor and the second input of the second element And the output transceiver0 five 0 five The device is an information output device and is connected to the first input of the secondary of the OR element, the output of which is connected to the second input of the receiver’s call site, the output of which is connected to the interrupt output of the device, the second input of the second po | -o element OR is connected to the second high-end pulse distributor, to the second input of the pause indicator and to the third interrupt node, the fourth input the third input of the node through the second element is NOT connected to the second input of the first element AND to the third input of the second element AND, the fourth input of the node is connected to the first input of the OR-NOT element whose output is connected to the third input of the first AND element and to the fourth input of the second AND element , the second input of the element OR is NOT connected to the output of the first trigger and to the first output of the node, the fifth input of the node is under-. Koiroporo is connected to the output of the counter, the second is connected to the information input of the second swarm output and the fifth input of the trigger interrupt node, the output of the first element I is connected to the interrupt output and to the request - the delay element is connected to the first input of the device, respectively, the input of the OR element whose second entry start node is connected to a common highway. connected to the output of the second element And, 2. The device according to claim 1, characterized in that the output of the element OR is connected to a single ЧТ5 pause indicator contains one-shot 15 input of the first trigger and with clock torus, pulse generator, counter, first; input of the second trigger, the output of which the first and third comparison circuits, the delay element, the NOT element, two OR-NOT elements, the first input of the first element OR-NOT connected to the first input, the "pause indicator, the second input of which is connected to the second input of the first element OR NOT and to the first to the input of the second element OR NOT, the output of the first element OR NOT is connected to the input of the one-vibrator, the output of which is connected to the second input trigger register and to the input of the second element OR-NOT, the third input of the pulse generator, the output of which x | tto connected to the output of the generator connected to the clock input of the register, the impulses, the direct output of the one-vibrator whose black-out input is connected to the cut element is NOT connected to the reset input of the counting by the second input of the node and to the input of a single vibrator, the counting input of which is connected to the gate, the output of which is connected to the input the course of the second element OR NOT, the first 30 reset the second trigger, a single input is the second output of the node, the reset inputs of the first and second triggers are connected to the reset input of the device. 4. A device according to claim 1, characterized in that the receiver call node contains a NOT element, two flip-flops, a register, a single-oscillator, a comparison circuit and a pulse generator, the first input of the node being NOT connected to the reset inputs of the first | groups of the counter are connected to the inputs of the same-name comparison circuits, whose input inputs are connected respectively to the first, first, and through the element to the second output of the pa indicator, are connected to the output of the NOT element, the output of the second trigger is connected to the input start pulse generator, the register output is connected to the input of the comparison circuit, the output of which is connected to the single input The inverse output of the one-shot co-35 of the second trigger, the output of which is with the fourth output of the node output indicator. n $ bonds. The device according to claim 1, characterized by 3. The device according to claim 1, characterized in that the start-up node contains an element 4to; the interrupt node contains two AND-NOT elements, a counter and a comparison circuit, and that is NOT, an element OR-NOT., an element NOT, an element input 40 is connected to the first input a delay element, two elements AND, two triggers, an element OR, the first input of the node is connected to the first input of the first element AND and through the first element NOT first entrance The second element And the second input node is connected to the second input of the second element And, the course of the node. AND IS, the second input and output of which are connected respectively to the output of the comparison circuit and to the counting input of the counter, the outputs of which are connected to the inputs of the comparison circuit, the output of which is the input of the first trigger and the clock input of the second trigger; trigger register and with the input of the pulse generator, the output of which is the second output of the node, the reset inputs of the first and second triggers are connected to the reset input of the device. 4. The device according to claim 1, characterized in that the receiver call node contains a NOT element, two flip-flops, a register, a single-vibrator, a comparison circuit and a pulse generator, wherein the first input of the node is NOT connected to the reset inputs of the node through the element the output element is NOT, the output of the second trigger is connected to the input start pulse generator, the register output is connected to the input of the comparison circuit, the output of which is connected to the single input  the second trigger, the output of which is the output of the node. the node input is connected to the first input by the node elekhod. is NOT, the second input and output of which are connected respectively to the output of the comparison circuit and to the counting input of the counter, the outputs of which are connected to the inputs of the comparison circuit whose output is you / yrg. one L. J (Ri.5 Q one 41 2 fig a