SU1383501A1 - Displacement-to-code converter - Google Patents

Abstract

The invention relates to automation and computing and allows for improved accuracy and speed. For this purpose, from the device containing the differential amplifier, current comparators, current switches with direct and inverse outputs, current sources, control unit, such elements are introduced that introduce additional errors, such as voltage subtractors and reference voltage sources. , the comparison in the proposed device is carried out in low-resistance circuits, and a differential amplifier is used to transform the high-resistance input circuit into a low-resistance one. 2 Il.

Description

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This invention relates to automation and computing.

The aim of the invention is to improve the accuracy and speed,

FIG. 1 shows a functional diagram of a three-bit analog-to-digital converter (ADC); in fig. 2- output characteristic of the differential amplifier.

The device contains a differential amplifier 1, comparators 2-4 currents, keys 5 and 6 currents with direct and inverse outputs, sources 7 and 8

current, control unit 9, bus 10, reference voltage, bus 11 and 12, reference voltage, output bus 13 - 15, bus 16 Start. The differential amplifier and current sources represent the inflow current devices.

The total number of cascades for a p-bit ADC is equal to p. The ADC converts the analog signal to a binary positional code. Transformation is conducted, starting with the older bit, n, and.

The device works as follows.

The input 10 of differential amplifier 1 receives an analog voltage signal, which in differential amplifier 1 is converted to interconnected current signals, representing direct (Inp) and inverse (IMK) currents (Fig. 2). In this case, a direct output current (") flows through the first current input of the comparator 2, and a differential current 1 flows inversely through the second current input of the same comparator. In the absence of a start signal at input 14, the converter is in the initial state. The control inputs of the comparators 2-4 do not receive high level control potentials. In this case, the state of the converter is undefined. The code at the ADC output does not reflect the actual value of the input analog signal. Direct current dnp) and inverse (l) currents of the differential amplifier 1, respectively, flow through the electrical circuits of the first and second inputs of the current comparator 2, respectively, currents that are sums of the differential current amplifier 1 and the current flow through the first and second inputs of the comparators 3 and 4 opon current sources. Let the moment

.

0

&

12

t, the Start signal is applied to the input of the control unit 9, then at the time point, the control input of the current comparator 2 from the control unit 9 receives a high level control signal (UUP-), which actuates this comparator. The current comparator 2 compares the currents Iqp and the currents flowing through the input circuits (figure 2). When the ratio of the currents at the output of the comparator 2 is set, the voltage corresponds to logical 1, and at the ratio of the currents, the output of the comparator 2 is set to logical O. If the output of the comparator 2, from which the current key 5 is controlled, is set to

then completely

opens the direct output of the current key 5, and all the current of the current source 7 (1y), representing the weight of the most significant bit of the code, flows through the direct output of the current key 5 and is added to the inverse current I j of the differential force. 1. Then the current (1) at the second input of the comparator 3 is the sum of the currents I is not-Z - T If the output of the comparator 2 is set to O, the inverse output of the current key 5 is opened, and the entire current of the current source 7 flows through the inverse output of the current key 5 is added to the current flowing through the first input of the comparator 2. Then the current dnp,) at the first input of the comparator is the total current "- ,, fI" +1. code bit and set the current mode in comparator 3 to compare no.

The result of the comparison in the comparator is remembered for the duration of the preservation of the potential of a high level at its control input.

At time tj, the control input of the comparator 3 receives a control potential of high level

and

control

. Comparator 3 compares currents

I prz and flowing through its inputs, respectively. If the current is 1prz Ij, then a logical G is set at the output of the comparator 3, and a logical O is set at I pree I imto. For logical 1, a direct output opens at the output of comparator 3, and for logical 0 1 at the output of the source 8 current, current Ig,

The current flowing through the forward output of the switch 6 is added to the current from the second output of the comparator 3, and a total current flows to the second input of the comparator 4. With logical O at the output of comparator 3, the current of source 8 flowing through the inverse output of switch 6 is added to the current from the first output of comparator 3, as a result of which the current will be I, + Ig. As a result of the second comparison, the value of the second bit of the code is determined and the current mode is set at the inputs of comparator 4. The result of the comparison in comparator 3 is memorized.

At time t, the control signal 4 is supplied to the input of comparator 4 Comparator 4 compares the currents

I n (, 4 and 1 Inch- P 1pr4 1i + output 15 is set to logical 1, and when, the output is set to logical O. The result of the comparison is remembered. As a result of the third comparison, the lowest bit of the code is determined. B time interval tj-tg code with The ADC is read. At time tg, the control signal is removed, from the converter, and the converter returns to its initial state.

one

Total current differential

Amplifier 1 over the entire change interval of the input voltage must be equal to the ratio

Lnp

+ 1 ,, + 1g + 1, + ... + 1 „., + 21n.

where i ,,, „, ..., i„ is the discharge.

weight currents. The index unit corresponds to the highest code discharge, and the index n corresponds to the younger current discharge.

Claims (1)

Invention Formula A cascade analog-to-digital converter containing n-1 current sources, where n is the number of converter stages, n-1 current switches, characterized in that, in order to improve accuracy and speed, n current comparators, a differential amplifier and a control unit, the input of which is a Start bus, and the outputs are connected to the control inputs of the respective current comparators, the first and second outputs of the i-ro current comparator, except the last, are combined with the corresponding outputs of the i-ro current switch and connected to the corresponding inputs The i + 1 st current comparator, and the first and second outputs of the last current comparator are the first reference voltage bus, the third outputs of the current comparators are Y. LINE and are connected to the control inputs of the corresponding current switches, whose inputs connected to the outputs of the respective current sources, the first and second inputs of the first current comparator being connected to the corresponding outputs of the differential amplifier, the first input of which is an input bus, and the second input - the second reference bus on prine YU 1 eight