SU1381719A1 - Device for detecting and correcting errors in reed - solomon codes - Google Patents

Abstract

The invention relates to computing. When used in specialized computer systems where an external computer memory is required for errors, the device can be simplified and its performance improved by reducing the initial delay when the Reed- code symbols are interleaved (wahnomon. The external memory device is looking for errors in the external memory syndromes, blocks 2.3 of buffer memory, block 5 transformations of syndromes, calculator 6 errors, switch 7 and block 8 modulo-2 adders. Leadar to the introduction of block 4 of buffer memory and special complements calculator residues 1 and syndromes in a device is provided for the desired degree of interleaving za1tity of packet errors, and symbol processing modes encoding and decoding is performed without prior storage 5 yl;.. of

Description

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The invention relates to computing and can be used in specialized computer systems where the external memory of the PCB is required to prevent errors.

The purpose of the invention is to simplify the device and improve speed by reducing the initial delay when interleaving the symbols of the Rhid-Solomon code.

Fig. 1 shows a block diagram of a device for detecting and correcting errors in Reed-Solomon codes; FIG. 2 is a block diagram of a calculator of residues and syndromes for the case of interleaving of four basic code words (15.11) in Reed-Solomon code symbols; Fig. 3 is a diagram of the processing unit of the syndromes, for the same case; 4 and 5 are functional diagrams of the first, fourth and fifth, eighth, and eighth code converters in the residual calculator and syndromes calculator for this case, respectively.

The device for detecting and correcting errors in Reed-Solomon codes contains calculator 1 residues and syndromes, first, second and third blocks 2–4 of the buffer memory, block 5 of the transformation of syndromes, calculator, 6 errors, switch 7, block 8 modulo adders two, information inputs 9, first to fourth control inputs 10-13, first and second clock inputs 14 and outputs 15,

The calculator 1 of residues and syndromes (figure 2) for the case of interleaving four basic words is performed on the first - fourth registers 16-19, the first - fourth blocks 2 () - 23 nt adders module two, the first - seventh blocks 24 - 30 switching, the first - the eighth converter 31-38 of the code and the first and second blocks 39 and 40 of the elements AND; The calculator also contains the second information inputs 41 (the first information inputs are the information inputs 9) ,. the first and second entrances 42 and 43,

Blocks 2-4 of the buffer memory can be performed, for example, on RAM.

The syndromes conversion unit 5 (Fig. 3) for the case of interleaving four base words is performed on the first fourth registers 44-47 and the first to fourth converters 48-51 of the code. Clock 5 has the first and second information inputs 52 and 53.

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The calculator 6 errors performed in the same way as in the prototype, and works on the same algorithm.

The first - the fourth converters 31-34 of the code (figure 4) calculator 1 residues and syndromes are made on the elements of the ISUPOLCAPLE OR 54. Fifth - the eighth converters 35-38 of the code of the calculator 1 residues and syndromes and the first - fourth converters 48-51 of the code of block 5 also made on the elements of SUDEVOCHARVDE OR 54 (figure 5). The above implementation of the transducers provides the multiplication of the input code of characters by constant coefficients in the field (IF (2)), which are the roots of the generating polynomial (for the given example).

The device for detecting and correcting errors in Reed-Solomon codes works as follows.

The signals to the clock inputs 14.1 and 14.2 come with a shift in half period. In the coding mode, an information sequence of forty-four characters (176 bits), symbolically forty-four cycles, enters simultaneously the computer 1 residues and syndromes and the second block 3 of the buffer memory. Preliminary, the scheme of calculator 1 of residues and syndromes is translated by a signal at the inputs of IO and 13 by blocks 24-30 into an encoder scheme. In this case, the outputs of the converters 31-34 of the code are connected by the switching blocks 24-27 to the first inputs of the blocks 20-23 of the adders, and the outputs of the registers 16-18 to the second inputs of the blocks 21-23. The encoder circuit is constructed according to the scheme of dividing the polynomial of the information part into the generating polynomial with the difference that the result of calculations in each clock cycle, obtained at the outputs of blocks 20-23 of adders, is recorded in the corresponding cell of the first block 2 of the buffer memory depending on the number of the processed basic code word or the corresponding number of the input character.

In the proposed device for ko-. For information information, a generalized code word of 60 characters (240 bits) is used, obtained by interleaving four basic code words (15.11) in Reed-Solomon code symbols. The generator polynomial g (x) of the base code has the following form:

g (x) (x-ci) (x -) () (x-oi) - x oc °,

where oC is a primitive element of finite

Galois field (; K (2); X is an arbitrary element of a finite field.

The first block 2 of the buffer memory in the encoding mode is designed to store four partial residues from dividing the information polynomial of each basic code word by forming a polynomial.

Interleaving is accomplished in the following way: the first, fifth, nine ..., forty-first characters of the information sequence are the first, second, third,..,., Eleventh characters of the first basic code word, respectively; the second, sixth, ninth, tenth, .. forty-second characters of the information sequence, respectively

first, second, third one

and the second character of the second base code word; the third, seventh, eleventh, ..., forty-third symbols of the information sequence are respectively the first, second,

third odd characters

the third base code word; the fourth, eighth, twelfth, ... forty-fourth symbols of the information sequence are, respectively, the first, second, third, .. ,, eleven symbols of the fourth basic code word.

The first cell of the first block 2 of the buAer memory stores the partial remainder of the first basic code word, the second cell contains the partial residual of the second basic code word, the third cell contains the partial remainder of the third basic code word, and in the fourth cell the remainder of the fourth basic code word is partial.

Each cycle of operation of the device consists of sixty cycles. The first sixteen clocks block 40 elements And is closed and the feedback circuit of the “–1 encoder does not work (open). Block 39 elements And open. The process of loading and unloading four cells of the first block 2 of the buffer memory is carried out. In the first, fifth, ninth and thirteenth cycles, the first input of the transmitter 1 is received, respectively

The first, fifth, ninth and thirteenth characters of the information sequence, which are simultaneously stored in the corresponding cells of the second buffer memory block 3, and the contents of the first cell of the first buffer memory block 2, which contains the control characters of the first the basic Reed-Solomon code of the previous generalized code word. In each of these cycles, the input symbols that arrive at the second group of inputs of the calculator 1 are rewritten into its corresponding registers 16-19. The input symbol, which is fed to the inputs 9, through the block 39 elements AND and the contents of the registers 16-18, respectively, through the switching blocks 28-30, arrive at the second inputs of the corresponding blocks 20-23 modulo-two adders. Zero symbols arrive at the first inputs of these blocks 20-23 through the switching blocks 24-27, since the block 40 of the AND elements is closed in feedback.

Thus, the input symbol and the contents of the previous registers 16-18 are transferred to the output group 43 of the calculator 1. (the engine is executed until the senior symbol of the information sequence is written into the last register 19. At the end of each of these cycles, information from the output group 43 of the calculator I is fed to the first inputs of the first block 2 of the buffer memory and stored in its first cell. (The content of the last register 19 goes to the outputs 42 of the calculator 1 and through the switch 7 and the block 8 modulo-two adders are fed to the outputs of the device 15. In the first, fifth, ninth and thirteenth clock cycles at the outputs of the device 15, respectively The twelfth, thirteenth, fourteenth, and fifth (check) characters of the first Reed-Solomon base code, which are the forty-fifth, forty-ninth, fifty and three and fifty-seventh characters of the previous generalized code word, and the first forty-four The information symbols were already transferred from block 3 of the buffer memory through block 8 to the outputs 15 of the device in the last forty-four cycles of the previous operation cycle.

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In each and the rest of the clock cycles, the computer I scheme works similarly to the first, fifth, nineth, and thirteenth clock cycles. The only difference is that at the end of each of the second, sixth, tenth, and fourteenth cycles, the information from the output group 43 of the calculator 1 is stored in the second cell of block 2, in the third, seventh, eleventh, and fifteenth cycles - in the third cell of block 2 , and in the fourth, eighth, twelfth, and sixteenth cycles, in the fourth cell of the first block 2 of the buffer memory. In this case, the output of the device 15 receives, respectively, the twelfth, thirteenth, fourteenth and fifteenth (control) characters of the second, third and fourth basic Reed-Solomon codes.

At the end of the data of the Sixteen clocks of loading and unloading the cells of the first block 2 of memory, the block of 40 elements And in the feedback of the calculator 1 is closed by a signal from input 12. During the next forty four clocks in the calculator 1, the control characters of the four basic Reed codes are calculated -Solomona of the following generalized code word. At the same time, the first twenty-eight acts are a block of 39 elements AND opened with a signal at input 11. In each of these twenty-eight clock cycles, the next information symbol enters the inputs of calculator 1 The sequence of sequences that is simultaneously stored in the corresponding cell of the second block 3 of the buffer memory, and the group of inputs 41, depending on the number of the input symbol (the number of the base code word being processed), receives the contents of the corresponding cell of the first block 2 of the buffer unit in which a partial remainder of dividing the information polynomial of the processed base codeword by the generator polynomial is stored. The input symbols that arrive at input group 41 of calculator 1 are rewritten into its corresponding registers 16-19. The input symbol, which arrives at the input of the calculator I, through the block 39 of the elements AND and the contents of the registers 16-18, respectively, the switching blocks 28-30 arrive at the first inputs of the corresponding blocks 20-23 of the adders. (Contents of the last re

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The horn 19 through the block of 40 elements And in the feedback comes to the converters 31-34 of the code, the output information of which through the blocks 24-27 of the switching goes to the second inputs of the corresponding P1 blocks 20-23 of adders. At the end of each of these cycles, information from the group of outputs 43 of calculator 1, which are connected to the outputs of blocks 20-23 of adders, goes to the group of inputs of the first block 2 of the buffer memory and is stored in its corresponding cell depending on the number of the processed base code word ( input character). Then the next cycle of the device operation begins.

At the end of the twenty-eight clock cycles, the block of 39 elements is locked at input 1. For the next sixteen clock cycles, the information polynomial of each basic code word is continued to be divided into a constituent polynomial, which corresponds to the information polynomial shift of each of the four basic code words by four bits in side of the stargun polynomial. At the end of these sixteen clock cycles, the encoding process is completed (calculation of the control characters of the four basic codes of the ReD Solomon generalized codeword).

Simultaneously with the calculation of the control characters of the four basic Reed-Solomon codes of the generalized code word, during the last forty-four cycles of this cycle, the information symbols of the same coded code word are output from the second block 3 of the buffer memory through the block 8 adders to the device outputs 15. In the seventeenth clock cycle at the output: device 15, the first symbol of the information sequence arrives, in the eighteenth clock cycle the second symbol of the information sequence, in the nineteenth clock cycle the third symbol of the information sequence and so on, and in the sixty cycle the forty fourth symbol of the information sequence. starts the next cycle of the device.

During the first thirteen clock cycles of the next cycle of operation during the reception of the first sixteen characters of the information sequence of the next generalized code word from the calculator 1 through the switch 7 and

The block 8 of the adders at the outputs of the 1.S device as described above outputs the calculated control characters of the four basic Reed-Solomon codes of the previous generalized codeword, therefore the initial delay in the coding mode is sixteen clock cycles or 16/60 A / 15 of the generalized codeword.

In the decoding mode, a generic code word 60 characters long (240 bits), read from the external memory, symbolically for 60 cycles goes to the calculator 1 of residues and syndromes and at the same time to the second block 3 of the buffer memory; syndromes by the signal at inputs 10 and 13 are transferred to the calculator circuit of syndromes. The outputs of each of the switching blocks 28-30 are connected to its second inputs, the outputs of each of the switching blocks 7Л-А1 to the first

its inputs during the first four bars, and then to its second inputs. The syndrome calculator circuit is constructed according to the Horner scheme for calculating the code polynom ohms values in its root C with, and with the difference that the result of the calculations in each clock cycle generated at the outputs of the 20-.3 modulo-two adders, is stored in the corresponding cell of the first block 2 of the buffer memory depending on the number of the input symbol (the number of the base code word being processed).

The first block 2 of the buffer memory in the decoding mode is designed to store the calculated intermediate results, which is the values of the part of the code polynomial of each basic code elephant in its roots. The distribution of the cells of the first block 2 of the buffer memory for the four basic code words is carried out similarly to the coding mode.

Each cycle of operation of the device consists of sixty cycles. The input unit of the 39 elements And the circuit of the calculator 1 is open. The first four cycles of a block of 40 elements And, in feedback, the outputs of each of the switching blocks 24-27 are closed connected to its first inputs. The process of loading and unloading four cells of the first block 2 of the buffer memory is carried out. N each of these measures the contents of the cells.

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The first buffer memory unit 2, each of which stores the four syndromes of the corresponding basic Reed-Solomon code of the preceding generalized code word, enters the first inputs of the syndrome conversion unit 3 and rewrites into its registers 44-47. In this case, in the first cycle, the syndromes of the first basic codeword are read out from the first cell, in the second cycle, the second basic codeword are syndromes from the second cell; in the third cycle from the third cell, syndromes of the third basic code word; in the fourth cycle from the fourth cell, syndromes of the fourth basic code word.

At the same time, in the first, second, third, and fourth clock cycles, the first, second, third, and fourth characters of the next generalized code word, which are stored in the corresponding cells of the second buffer memory unit 3, arrive at the inputs of calculator 1, respectively. The input symbol enters through a block of 39 elements And and blocks 28-30 switching to the first inputs of blocks 20-23 adders. Zero symbols arrive at the second inputs of blocks 20-23 through switching blocks 24-27, since the AND block of 40 elements is closed in feedback, and the outputs of the switching blocks 24-27 are connected to their first inputs. The output symbol of the generalized code word is transmitted to the output group 43 of the calculator 1 from the outputs of the blocks 20-23 of the adders. At the end of each of these cycles, information from the group of outputs 43 of calculator 1 arrives at the outputs of the first block 2 of the buffer memory and is stored in its corresponding cell depending on the number of the input symbol of the generic code word (the first character is in the first cell, the second sy. in the second cell, the third symbol - in the third cell, the fourth symbol - in the fourth cell).

At the end of these four cycles of loading and unloading four cells of the first block 2 of the buffer memory, the outputs of each of the switching blocks 24-27 are connected to its second inputs. During the next five six cycles in the circuit of calculator 1, the calculation of the four syndromes of each basic ReedSolomon code is summarized} of the 1st code word. In each of these cycles, the next character of the generalized code word is sent to the inputs of the calculator 1, which is simultaneously stored in the corresponding cell of the second block 3 of the buffer memory, and the group of 41 inputs, depending on the number of the input character (the number of the base code word being processed), is received the first block 2 of the buffer memory. The input symbols that enter the group of inputs 41 of the calculator 1 are rewritten in accordance with its registers 16-19. The input symbol through the block of 39 elements And and through the blocks 28-30 of the combination enters the first inputs of the blocks 20-23 of adders. The contents of each of the registers 16-19 is fed to the corresponding converter 35-38 code. The output information of the latter through the switching blocks 24-27 goes to the second inputs of the corresponding blocks 20-23 dryers. At the end of each and these clock cycles, the information from the outputs 43 of the calculator 1 is fed to the inputs of the first block 2 of the buffer memory and is stored in its corresponding cell, depending on the number of the base code word being processed (the number of the input symbol). At the end of the fifth test period, the next cycle of operation of the calculator begins.

Simultaneously with the operation of the circuit of the calculator 1 and the second block 3 of the buffer memory, the symbols of the previous generalized code word are output, and in block 5 of the syndromes conversion and the calculator 6 errors are judged for the same cycle, the error value for the given output is MOF-Q . In block 5, the transformation of syndromes causes the cyclical shift of the four syndromes of each basic Reed-Solomon code of the previous obbochtsenny code word by multiplying in blocks 48-31 of these syndromes, respectively (L, oi, (roots of the polynomial). In the calculator, 6 errors on the converted syndromes In the same cycle, the error value for the given character is determined.

In each step of the operation of the device from the pair of block 3 buffer memory

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the next character of the previous generalized code word is output, which is fed to the first inputs of the block 8 modulo two adders. At the same time, the registers 44-47 of the syndromes conversion unit 5 rewrite the information from its first inputs 52 in the first four cycles of loading the cells of the third block 4 of the buffer memory or from its second inputs 53 in the remaining five six cycles of this work cycle. The contents of the corresponding cell of the third block 4 of the buffer memory are fed to its second inputs 53, depending on the number of the processed Reed-Solomon base code (the number of the output symbol) of the previous generalized code word. The distribution of the cells of the third block 4 of the buffer memory for the four basic code words is carried out similarly to the first block 2 of the buffer memory. The contents of each of the registers 44-47 of block 5 are fed to the corresponding converter, 48-51 codes. Information from the outputs of block 5 is fed to the inputs of the third block 4 of the buffer memory and is stored in its corresponding cell, depending on the number of the processed basic Reed-Solomon code of the previous generalized code word. At the same time, information from the outputs of the syndromes conversion unit 5 is fed to the inputs of the calculator 6 errors. The value of the error from its outputs, calculated in the calculator 6, through the switch 7 is fed to the second inputs of the modulo-8 block 8 o. Block 8 of the adders corrects the output symbol by adding it to the opibka value. In the first cycle, the first symbol of the previous generalized code word arrives at the device outputs 15, the second symbol receives the second symbol, the third symbol enters the third one and so on, and the forty-fourth symbol of the information part of the generalized codeword in the forty-fourth cycle.

Thus, the initial delay in the decoding mode is one device operation cycle corresponding to the transmission time of one generalized codeword.

The proposed device for detecting and correcting errors in codes 1 and ida-Saul:) does not allow

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correct at the interleaved degree, equal to 4, one error packet up to 29 bits or two error packets of 13 bits in each generalized code word of .40 bits long (the number of correctable basic error code 2, character length 4 bits),

Compared with the known, the proposed device is simplified by about 1.65 times.

The initial delay introduced by the proposed device when interleaving the symbols of the basic Reed-Solomon codes in the generic code word in the coding mode is 4/15 generalized code word, in decoding mode - one generalized code word (in known devices there are two or three generalized code words the words).

In the proposed device, without changing its operating part, the degree of symbol interleaving of the information sequence can be changed, i.e. the number of basic Reed-Solomon codes as part of a generalized code word, while it suffices to change the capacitance of blocks 2-4 of the buffer memory and the number of ticks in the cycle

the number of base code words), the first -G blocks of adders modulo two first and second blocks of elements And, the outputs of the first block of elements And connected with the corresponding first input of the first block of adders modulo two, the outputs of the K-th register are connected to the corresponding information inputs the second block of the And elements and the second information inputs of the switch; the information inputs of the first block of elements And are combined with the corresponding information inputs of the buffer memory block and are the formation inputs of the device, clock inputs the first and second blocks of the buffer memory are combined and are the first clock input of the device; the clock inputs of the conversion unit of the syndromes and the calculator are faulty and the synchronization inputs of the first — K-g registers of the residual and syndromes calculator are the second clock input of the device The control input of the switch and the control inputs of the first and second blocks of the elements And the calculator of residuals and synomas are, respectively, device revisions. For example, if jQ vy - third control inputs

ki 2-4 buffer memory build on integrated circuits such as K531RU8P, you can increase the degree of interleaving from four to sixteen without additional costs for the implementation of the remaining blocks, and with the degree of interleaving equal to sixteen, the proposed device allows you to correct the error package 125 bits or two 61-bit packets in a 960-bit generalized word.

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device, characterized in that, in order to simplify the device and increase speed by reducing the initial delay when interleaving the symbols of the Reed-Solomon code, a third block of the buffer memory is inserted into the device, the first (2К-1) - the first switching blocks and the first (2K) code converters, the output of the () -th (2K-1) -th switching blocks are connected to the first information inputs of the second K-th block of modulators, respectively connected to the appropriate in The first - K th code converters, the outputs of which are connected to the corresponding first informatunal inputs of the same switching unit, the outputs of which are connected to the corresponding second inputs of the same name modulo two adders, the outputs of the first - (K-1) th registers are connected to the first information inputs, respectively (Ktl) - th - {2K-1) -th switching blocks, and respectively (K + 1) -th - (2K-1) -th code converters - to

Claims (1)

Invention Formula The device for detecting and correcting errors in Reed-Solomon codes, which contains the syndromes conversion unit, the first block of buffer memory, the error calculator, whose outputs are connected to the corresponding first information inputs of the switch, the second block of buffer memory, the outputs of which are connected to the corresponding First inputs of the block modulo-two adders, the outputs of which are the outputs of the device, and the calculator of residues and syndromes, including the first, the K-th registers (K 10 5 8171912 the number of base code words), the first -G blocks of adders modulo two and the first and second blocks of elements And, the outputs of the first block of elements And connected to the corresponding first inputs of the first block of adders modulo two, the outputs of the K-th register are connected to the corresponding information inputs the second block of the And elements and the second information inputs of the switch, the information inputs of the first block of the elements And are combined with the corresponding information inputs of the buffer memory block and are the information inputs of the devices a, the clock inputs of the first and second blocks of the buffer memory are combined and are the first clock input of the device, the clock inputs of the syndromes conversion unit and the error calculator and the synchronization inputs of the first — K-th register of the residual and syndromes calculator are combined and are the second clock input of the device, The control input of the switch and the control inputs of the first and second blocks of elements And the residual calculator and syndromes are respectively the first 20 25  jQvm - the third control inputs five 0 five 0 five device, characterized in that, in order to simplify the device and increase speed by reducing the initial delay when interleaving the symbols of the Reed-Solomon code, the third block of the buffer memory is inserted into the device, the first (2K-1) are entered into the residual calculator and syndromes -th switching blocks and the first - (2K) -th code converters, outputs. () -th - (2K-1) -th switching blocks are connected to the first information inputs of the second - K-th modulo adders block, two outputs of the second block of elements And are connected to the corresponding inputs of the first - K-th code converters, the outputs of which connected to the corresponding first computer inputs of the same switching unit, the outputs of which are connected to the corresponding second inputs of the same module adders modulo two, the outputs of the first (K-1) -th registers are connected to the first information inputs respectively (K-t-l) -th - {2K-1) -th switching blocks and through respectively (K + 1) -th - (2K-1) -th code converters - to 13i the second information inputs of the first, respectively (Kl) -ro switching units, the inputs and outputs of the (2K) th code converter are connected respectively to the outputs of the K-th register and the second information inputs of the K-th switching unit, the second inputs (K + 1 ) -th - (.K-1) -th switching blocks, respectively, are combined and connected to the outputs of the first block of elements I, controlling; and the inputs of the first K-th switching blocks are combined and connected to the first control input of the device, controlling the inputs (K + 1) th - (2K-l) -ro switching units are combined and are the fourth control input of the device, the output of the first - K-th block of modulo-two calculators of residuals and syndromes are connected to the corresponding information inputs of the first block of the buffer memory, the outputs of which are four 14 They are connected to the corresponding first information inputs of the syndromes conversion unit and the information inputs of the first — K-th register of the residual calculator and syndromes; the outputs of the syndromes conversion unit are connected to the corresponding 1 D1m information inputs of the error calculator and the third block of the buffer memory, the outputs of which are connected to the corresponding second information the inputs of the syndromes conversion unit, the switch outputs are connected to the corresponding 1 No. 1m second inputs of the modulo-two adders, clock the input of the third block of the buffer memory is connected to the first clock input of the device, the control input of the syndication conversion unit is connected to the second control input of the device. 52 Sj (fft / dz  I “B "Ci 5 years