SU1381494A1 - Device for calculating n-th root - Google Patents

Abstract

The invention relates to digital computing and can be applied in digital computers and in the construction of specialized computing devices. The purpose of the invention is to increase speed while simultaneously expanding the class of problems to be solved due to the possibility of processing numbers in the form of floating point. The device contains a register of 3 exponents, a register of 4 bases, encoders 5, 6 addresses, memory blocks 7–9, multipliers 10, 11, switch 12, adders 13.14, order alignment block 15, control block 16, result register 17. The calculation of the p-th root in the device is performed by calculating the polynomial with the coefficients previously calculated and stored in the memory. (P

Description

18

with

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N-4

with

N

(puff.l

The invention relates to digital computing and can be applied in digital computers and in the construction of specialized computing devices.

The purpose of the invention is to increase the speed of the device while simultaneously expanding the class of tasks by processing numbers in the floating-point form.

The calculation of the root of the nth degree in the proposed device is made

by calculating the polynomial

with pre-calculated and memory coefficients

y-f (xii) (i)

vfe- ;.

When presenting the argument with fixed or wakiza and approximation

f (x)

a polynomial of the first degree, with an accuracy of no worse than 10, is calculated respectively by the following algorithms:

47 A; X; - B; for fixed-point numbers

H- ((PRC /. LPx

x (A; t + B; H2

for floating point numbers, where A; and B; - coefficients for a given degree of root and

a radical expression;

2 w.

- mantissa of the radical; X is a radical expression; PX - the dock of the radicard

expressions;

n is the exponent of the coefficient - H, where i O, 1.2 ... 12 Values, as well as the coefficients A; and Bj are calculated in advance and stored in memory.

FIG. 1 shows a block diagram of a device for calculating a root of degree n; in fig. 2 is a block alignment circuit diagram; in fig. 3 and 4 - options for the implementation of the switch and shifter, respectively.

Q

five

0

five

0

five

0

five

0

five

The device for switching off the p-th root contains the first 1 and second 2 information inputs, the register of 3 degrees, the register of 4 bases, the encoder 5 and 6 addresses, memory blocks 7–9, multipliers 10 and 11, switch 12, adders 13 and 14, order alignment unit 15, control unit 16, result register 17, result output 18, order alignment block inputs 19-23, adder 24, encoders 25 and 26, shifters 27 and 28, alignment block outputs 29-31 orders, inputs 32-35 of switch 36 with output 37 and inputs 38-44 of shifters 45 with output 46.

A device for calculating a p-th root works as follows.

Input 1 receives the exponent of the root, and input 2 receives the base in binary code. Depending on the contents of the root degree and the sub-root expression and upon the arrival of the control signal from the second output of the control unit, the first encoder 5 generates the address and information is selected from the first memory unit 7 to the address. The contents of register 4, the second encoder 6 simultaneously with the first encoder 5 generates

the address and the second 8 and third 9 memory blocks at this address are selected information of the coefficients A and B. On the first multiplier 10, the signal from the third output of the control unit 16 of the second memory block 8 is multiplied by A X. Then, from the output of the first multiplier 10 and The third memory block 9 receives the numbers on the order alignment unit 15 and, according to the signal from the fourth output of the control unit 16, the order alignment begins. If the numbers are in floating point form, the orders of the numbers are subtracted on the adder 24, i.e. from the order of the coefficient A, the order of the coefficient B is subtracted. Depending on the sign of the difference of the orders and the received private encoder 25 and 26, a shift code is determined, which is fed to the shifters 27 and 28, respectively. The numeric values of the mantis are supplied to the information inputs of the shifters. The mantissa is shifted, the order of which is smaller. After shifting the mantissa with a smaller order and transmitting the mantissa with a large order without

the shift, the information from the shift output 27 and 28 is fed to the input of the adder 13 and is summed, i.e. A; X + B; The sign bit from the output of the adder 24 is applied to the inputs 33 and 35 of the switch 36. Depending on the value of the sign bit, one of the AND schemes 36 of the switch 36 is opened and passes a larger order of numbers A; or in; to the second input of the second adder 14. The first input of the adder receives the order of expression 2. At the output of the adder 14, the resulting order is obtained.

The resultant mantissa is obtained at the output of the second multiplier 11, the first input of which receives the mantissa 2, and the second mantissa A; X + B ,. On the control signal coming from the fifth output of the control unit 16, the production is performed.

lead mantis. (A / X-t-B,) and the resultant mantissa at the second input is recorded in register 17, and the order at the first input of this register is recorded. If the root expression is represented in the fixed-point form, then the register 3, the address encoder 5, the memory block 7 and the adder 14 are not included in the operation, i.e. the control signals from the control block 16 do not come to them, and the block of 15 ° typing of orders and the second 11 multiplier become transparent, i.e. miss information without changing it. As a result, an algorithm of the form A; X-i Bj is executed.

Claims (2)

1. A device for calculating a p-th root, containing a base register, the recording resolution input of which is connected to the first output of the control unit, a switch, a first adder, a result register, characterized in that, in order to increase speed while simultaneously expanding the class of tasks to be solved floating-point processing of numbers, a degree indicator register, first and second address encoders, first to third memory blocks, first and second multipliers, second adder, and alphanumeric block Op orderings, connected by the relation information input and write enable input of register exponent Jq j5 20 25 on 35 40 ds 50 five connected respectively to the first information input of the device and to the first output of the control unit, information input 1 of the base register is the second information input of the device, the output of the exponent register and the output of the high-order group of the base register are connected to the first and second inputs of the first address encoder whose output is connected to the address input of the first memory block, the output of the second address encoder is connected to the address inputs of the second and third memory blocks, the output of the base register to the first inputs of the second address coder and the first multiplier, the third input of the first and second inputs of the second address coders, as well as the sample inputs of the first, second and third memory blocks are connected to the second output of the control unit, the output of the first memory block is connected to the inputs of the first operands The second adder and the second multiplier, the inputs of the second operands of which are connected to the outputs of the switch and the first adder, respectively, the first output of the second memory block is connected to the first information input of the switch and the first the formatting input of the order alignment unit, the second information input of which is connected to the output of the first multiplier, and the third information input of the order alignment unit and the second information input of the switch are connected to the first output of the third memory block, the second output of which is connected to the fourth information alignment block input The control input of the first multiplier is connected to the third output of the control unit, the fourth output of which is connected to the control inputs of the alignment unit in the order of and the first adder, the inputs of the first and second operands of which are connected to the first and second information outputs of the order alignment unit, the sign output of which is connected to the control input of the switch, the write enable inputs of the second adder, second multiplier and result register are connected to the fifth output of the control unit The outputs of the second adder and the second multiplier are connected respectively to the order and mantissa inputs of the result register, the output of which is the output of the device. 2. A device according to claim 1, characterized in that the order leveling block comprises an order combiner, first and second encoders and the first and second shifters, wherein the inputs of the first and second operands and the record resolution enable input of the order adder are respectively the first and third the information and control inputs of the block, the output of the character of the order adder is connected to the first inputs of the first and The second encoder is the sign output of the block, the first and second information outputs of the order adder are connected respectively to the second inputs of the first and second encoders, the outputs of which are connected to the control inputs of the first and second shifters, the input values of the orders of which are the second and fourth the information inputs of the block, the outputs of the first and second shifters are the first and second information outputs of the block. FIG. 2 Fig.Z Figm