SU1381492A1 - Divider - Google Patents

Abstract

The invention relates to computing and can be used autonomously or in conjunction with a digital computer to increase computational performance. The aim of the invention is to expand the scope of application by performing the division of complex numbers. Delivered intact. achieved by the fact that the device, including the first and second groups of adders 1 and two elements EXCEPTED OR 7, contains the third and fourth groups of adders 1, two groups of adders 2 intermediate calculations, groups of calculators 3, 6 values of bits, two groups of adders 4 residual definitions and a group of adders 5 defining values with corresponding links. 2 hp f-ly, 3 ill. che cl with:

Description

with

00

g

Hche

 / P / F I No.

Iduii

113814922

This invention relates to compute-EXCLUSIVE SHOCK OR 7, informational

technology and can be used with inputs 8-11 and outputs 12 and 13. It is called as part of a multiprocessor computer 3 values of bits

the computer as the speed of operation (Fig. 2) contains four adders

multifunction device-14 and subtractor 15., property. Calculator 6 bit values

(Fig. 3) contains three adders 14

The purpose of the invention is the extension of the obedient 15.

the field of application of the device for de-, Q The operation of a symmetrical device

laziness by doing a division of com-d. division numbers of complex numbers.

FIG. 1 shows a diagram of the device-211V x + iy (1)

dividing facilities for when c + jd

p 3 (n — resolution of presentation 5 is based on the following correlation of information); in fig. 2 and 3 - schematic diagrams x: calculators of the bits of the first and second groups, respectively, x. y -SlE, (2) (the numbers in brackets denote the numbers of c + d moves). 20 Write the expressions (2) in bitwise.

form like;

Device for dividing (Fig. 1)

 VV V „.. Vv V V 7u VV Vw UU V V

contains four groups of adders 1, ac + bd- (cc + dd) bc-ad- (cc-t-dd), (3) two groups of adders 2 intermediate computations, the first group of subtractors 25 values of bits, two and y in expression (3) we write

groups of adders 4 definitions of a-n-discharge equations, based on

tatkov, a group of adders 5 defined -an of which is determined by the corresponding values, the second group of subtractive i-e value (, 2 ,,

sliters 6 values of bits, elements-30 ..-, p).

S; -. 2- a. bd) 2- -}; i. ; ; V - .., s)

 . 2 (U - d)},. H; - ,, G ()

where if; .,. (. dd)

2- (U.1; „,,. P, 4, d; p.;.,.,.

. i; (five)

, dx (6)

2- - p; ,, 2- - | ; ... 2- - p;, d;

,, - dy

The algorithm for calculating the values of the ram-, bottom of equation (4) can be charges X, is similar and is written in each of:

g. r (i.iV-i; „; v; п .li + o v i (0

, „PH | i :: ° - 2- (Si. Sch. (,);,; -;; DRE ;;;:

 ,: - -Guide-e G.e-CH (2- - f; l f. S;.

2) g 1

t; 1 „at. (Lu, (8). And S

1 i (l) 1 (11 MI) (P

where x x -t-x, + y

The device for dividing (Fig. 1) works as follows. Values a, c, d and b, respectively, are input to input 8-9, after which a transient process takes place in the device circuit. After the end of the transition process, the output of the first adder 5 determines the values by expression (5) calculates the value 2, which is fed with a shift of 2 to the first input of the second adder 5, as well as to the second inputs of the first calculators 3 and 6 digits of the first and the second group, in each of which bit equations are modeled by expression (4). In this connection, at the outputs of the first calculators 3 and 6, the bits of the first and second groups calculate V (, i v (,)

respectively, the values of S and Sj, which are fed to the second inputs of the first adders 4 determine the residuals, and the values of the first bits x are formed at their bit outputs.

CHA (1) (g V V x, and y, for the ULTIMATE X, Y,

which are supplied to the outputs of the first bits 12, 13, 12 and 13 of the second 13 outputs and to the control inputs of the first adders 1 of the first, second, third and fourth groups, respectively. At this time, at the outputs of the first adders 1 of the first and second groups, according to expression (6), the values 2 р ° and 2 are formed, which are fed to the inputs of the first adder 2 intermediate calculations and with a shift of 2 to the first inputs of the second adders 1 of the first and second groups. At the outputs of the first adders 1 of the third and fourth groups, according to expression (7), the values 2 j and 2 are formed (I which arrive at the inputs of the first adder 2 intermediate

calculations and with a shift of 2 - to the first inputs of the third adders 1 40 of the third and fourth groups. Then, at the outputs of the second adders of 2 computations and with a shift, the 2nd inputs of the corresponding second adders of the third and fourth groups. At the outputs of the first adders 2 intermediate calculations of the first and second groups, expressions (6) and (7) calculate the values of 2 V and 2 V, which are received at the first inputs of the first adders 4, respectively, of the first and second groups, in which by interim calculations by expressions (6) and (7) determine the values 2 and 2 ,, that arrive at the first, to the first inputs of the second adders 4, determining the residuals of the first and second groups,

in which, according to the expression (4), the numbers (2 | Л (г1

residual values S

and s;

arriving at the first inputs of the third 50 calculators 3 and 6 of the bits of the first and second groups. Similarly, in each i-th adder 5, according to expression (5), the value, calculated at the first inputs of the i-th calculation is calculated: (I

and s

(I)

which transference (4) calculates the values of the 55 converters 3 and 6 of the bits of the first and second groups and with a shift of 2 to the first input of the subsequent (i + 1) -ro adder 5. In ix calculators 3 and 6 of the values of the bits of the first and second

are fed to the first inputs of the second solvers 3 and 6 of the bits of the first and second groups, respectively. Further

381492H

in the second adder, the 5 defining values from the expression (5) calculates l v

SL is the value of 2 y, which arrives at the second inputs of the second solvers 3 and 6 of the bits of the first and second groups, as well as with a shift of 2, at the first input of the third adder 5 defined values. In these 10 calculators of 3 and 6 values of ra: the set of the first and second groups, by expression (4), the second discharge equations are reproduced and the values of S and S 2 are determined, which arrive 15 at the Top Inputs of the second adders 4 determine the residues of the first and second groups, respectively, and on their bit outputs the values of the second bits of the sought values are formed, 20 which are supplied to the outputs of the second bits 12, 12 (and the first 12 and second 13 outputs and to the control inputs of the second adders 1 of the first, second, third and fourth group, respectively . In about 1 second adders of the first and second groups of vfazheniyu (6) are defined by two values | b 2 p ° and

which are fed to the inputs of the second adders 2 30 intermediate calculations of the first group and with a shift of 2 - to the first inputs of the third adders 1 of the same groups. At the outputs of the second adders of the third and fourth groups on the maturing;

2- Y

and

35 (7) values 2 are calculated (1

which enters silo inputs

2 intermediate T

second adder

calculations and with a shift of 2 - to the first inputs of the third adders 1 40 of the third and fourth groups. Next, at the outputs of the second adders 2, pass the residues of the first and second groups,

in which, according to the expression (4), the numbers (2 | Л (г1

residual values S

and s;

arriving at the first inputs of the third 50 calculators 3 and 6 of the bits of the first and second groups. Similarly, in each i-th adder 5, according to expression (5), the value, that arrives at the first inputs of the i-th subgroups by expression (A), is calculated, ie, the bit values of the desired vectors X, Y, which are received for ie, the bits of the first, and second, 13 outputs 12 and 13 and control inputs of adders 1 of the first, second, third and fourth groups. In the ix adders 1 of the first and second groups and in the iM adder 2 of the first group, by the expression (6), the value, which goes to the first input of the i-ro adder 2 intermediate calculations of the first group, is output, and by the output (D) is calculated the value of S arriving at the first input of (i + 1) -ro calculator 3 values of bits of the first group. Similarly, in the ix adders 1 of the third and fourth groups and in the i-th adder 2 intermediate calculations of the second group, by the expression (7), the value of S i available at the first input of the i-ro adder A for determining the residuals of the second group is calculated, the output of which by the expression (4 ) computes the value supplied to the first input (i + O-ro calculator of the bits of the second group. And, finally, in the nth adder 5, by the expression (5), the value that is fed to the second inputs of the nx is calculated calculators 3 and 5 values of bits, and on their discharge outputs are formed the nth lower bits .n (il u (z) y, y iskomk vectors x, y,

some enter the nth bits

12

ti)

13

WITH)

13

u

ko-12

first 12 and second 13 outputs. The signs of the sought-for variables X and Y are formed at the outputs of the first and second elements of the EX-OR 7 and arrive respectively at sign bits and 13 of the first 12 and second 13 outputs. Thus, for a time equal to the delay of the signal between the inputs and outputs of the elements, the desired values are formed at the first 12 and second 13 outputs of the device. y in the form of sets of COOT respectively. In addition, in the proposed device, the following functions can be reproduced:

at

Y be,

c 1 and d 0;

Y

be

at

 0;

Y

d

with b 0, a 1;

y - bld Y - 2-

with d 1;

0

five

0

depending on how the set of input data takes a zero or one value.

Claims (3)

1. A device for dividing, containing the first and second groups of adders and two elements EXCLUSIVE OR, 0 characterized in that, in order to expand the scope of application by performing the division of complex numbers, it contains the third and fourth groups of adders, two groups 5 adders of intermediate calculations, two groups of calculators of values of bits, two groups of adders of residual determination, a group of adders of defining values, with the outputs ix of adders (i 1,2, ..., n, n being the information width) of the first and second groups connected, respectively, to the inputs of the first and second terms of the i-th adder of intermediate calculations of the first group, the output of which is connected to the input of the first term of the i-th adder of determining the remainder of the first group; the outputs ix of the adders of the third and fourth groups are connected respectively venno to the inputs of the first and second terms i-ro adder intermediate computation of the second group, the output of which is connected to the input the first term of the 1st adder for determining the remainder of the second group, the outputs ix of the calculators of the bits of the first and second groups are connected to the inputs of the second term of the 1st adders for determining the residues of the first and second groups, respectively, whose outputs are connected to the first inputs (i + l) - x calculators of the values of the bits of the first and second groups, respectively, the output of the i-ro adder of the determining values of the group is connected to the second inputs of the i-th calculators of the values of the bits of the first and second groups and shifted by one bit in the direction of the younger ones rows - with vho7 The house of the first addends (i + 1) -ro of the adder of defining values of the group of the first and second bits of the i and the calculator of the bits of the first group are connected respectively to the first and second division inputs ix of the adders of the first and second groups and Yes, the first output of the device, the first and second bit outputs of the i-th calculator of the bits of the second group are connected respectively with the first and second inputs of the resolution of the i-th adders of the third and fourth groups and are the output of the i-th digit of the second output of devices , the output of the i-ro adder of the K-th group (K 1-4) is connected with a shift by one bit in the direction of the lower-order bits to the input of the first addend () -ro of the adder of the K-th group, the first information input of the device is connected to 21 bits in the direction of the lower bits with the third outputs tx of the calculators of the bits of the first and second groups, the second information input of the device is connected to the shift (21-1) bits towards the lower bits with the inputs of the second ix adders of the second and third groups, with a shift of 21 bits towards the lower bits ov - with the input of the second term of the 1st adder determining the group values, the input of the 1st bit of the second information input of the device is connected with the first control inputs 1 through X of the calculators of the bits of the first and second groups and with the first permission input of the i-th the adder of determining group values, the input (1 + 1) of the second information input of the device is connected to the singing inputs of the resolution ix of the mid-life adders of the first and second groups, the third information input of the device is connected with a shift by 2 (1-t) bits aside Well, the low-order bits with the inputs of the second components of the 1st adders of the first and fourth groups, with a shift of 21 bits towards the lower-order bits — with the input of the third term of the 1st adder, the determining values of the group, the input of the 1st bit of the third information the device’s input is connected to the second control inputs of the 1st calculator of the bits of the first y j 20 25 0 5 thirty 35 40 five eight and the second group and with the second resolution input of the i-ro adder defining group values, the input (1 + 1) -th bit of the third information input of the device is connected to the second resolution inputs ix of the adders of intermediate calculations of the first and second groups, the fourth information input of the device is connected with a shift by i bits towards the lower bits with the fourth inputs of the calculators of the bits of the first and second groups, the outputs of the sign bits of the first and second outputs of the device are connected respectively to the outputs of the first and volts Exclusive OR elements, the first inputs of which are combined and connected to the output of the sign bit of the first adder of the group defining values, the second inputs of the first and second elements of the EXCLUSIVE OR are connected respectively to the outputs of the sign bits of the first calculator of the values of the bits of the first and second groups. 2. The device according to claim 1, characterized in that the calculator of the values of the bits of the first group contains the cam of the adder and the calculator, and the inputs of the first and second components of the first adder are respectively the first and third inputs of the calculator of the values of bits, the first and second controls The input inputs of which are connected respectively to the resolution inputs of the first and second adders, the output of the first adder and the fourth input of the calculator of the bit values are connected respectively to the inputs of the first and second terms of the second sum an atom whose output is connected to the input of a decremented subtractor, the output of which is connected to a shift by one bit towards the lower bits, to the input of the first term of the third adder, the output of which is connected to the input of the first term of the fourth adder, the output of which is the output of the bit value calculator whose second input is connected to the input of the second term of the fourth adder and with a shift by one bit towards the lower bits - with the inputs of the second term of the third adder and the subtracted subtractor, the outputs of the sign bits of the second adder, the subtractor and The third adder is the sign bit output, the first and second bit outputs of the bit value calculator, respectively. 3. The device according to claim 1, wherein the calculator of the values of the bits of the second group contains three adders and two subtractors, and the inputs of the first and second terms of the first adder are the first and fourth inputs of the calculator of values of the bits, the third input of which is connected with the input of the readable first subtractor, the input of which is decremented is connected to the output of the first adder, the first and second control inputs of the calculator of bit values are connected respectively to the resolution inputs of the first adder and the first subtract atel whose output connected to the input of the decreasing second subtractor, whose output is connected with a shift by one bit towards the lower bits with the input of the first term of the second adder, the output of which is connected to the input of the first term of the third adder, the output of which is the output of the bit values calculator, the second input of which is connected to the input of the second term of the third adder and with a shift of one bit towards the lower bits - with the input of the second term of the second adder and with the input of the second subtrac rows of sign bits of the first and second subtracters and the second adder are respectively output sign bit, the first and second discharge dnymi value calculator outputs bits. cpusZ ABOUT Fig 5