SU1377756A1 - Peak detector - Google Patents

Abstract

The invention relates to the field of electrical measurements and can be used to measure the amplitude values of signals. The purpose of the invention is to improve the accuracy of the conversion. The peak detector contains an operational amplifier (V) 1, a controlled charge switch (K) 2, resistors 3 and 5, a storage capacitor 4 and diodes 6 and 7. The end of the resistor 7 is connected to a common SC ;; .), and the input bus connects to the non-inverting input Y I. Due to this, a positive charge, which occurs in the converter during the leading edge of the pulse, flows through the open K 2 to the power bus. At the end and the leading edge, K 2 is closed, and the negative charge arising in the converter during the falling edge of the pulse is distributed between the converter and the storage by capacitor 4. At the same time, a voltage appears at the detector output equal to the voltage on the storage capacitor 4 To increase the storage time of information between the input of the device and the non-inverting input, input 1 includes an additional capacitor 9, and parallel to the input, switch 10, which closes at the end of the pulse. 1 hp f-ly, 2 ill. with a. with

Description

The invention relates to electrical measurements and can be used to measure amplitude values of signals, for example, from piezoelectric impact parameters.

The purpose of the invention is to improve the accuracy of the conversion.

FIG. 1 shows a block diagram of a detector; in fig. 2 - the same, option.

The peak detector (Fig. 1) contains an operational amplifier 1, a controlled charge switch 2, the control input of which is connected to the output of the operational amplifier 1, the first output is from the power supply (-U), and the second output is through the first resistor 3 - with a common bus and the first tab of the storage capacitor 4 and the second output of the second resistor 5. The first electrode (cathode) of the first diode 6 is connected to the connection of switch 2 and resistor 3, and the second electrode (anode) to the non-inverting input of amplifier I, the second capacitor plate 4 and the input devices The first electrode (cathode) of the second diode 7 is connected to the output of the amplifier 1 and the second electrode (anode) - to the noninverting input of amplifier 1, the first terminal of the resistor 5 and the output device. The switch 8 reset is connected in parallel to the capacitor 4. The output of amplifier 1 is also connected to the auxiliary output of the device.

In addition, the device (Fig. 2) contains additional capacitor 9 and switch 10. Capacitor 9 is connected between the input of the device and the second plate of the capacitor 4, and switch 10 - between the input of the device and the common bus.

The device works as follows.

A positive polarity impulse arriving at the input of the device hits the non-inverting input of operational amplifier 1, as a result of which a positive voltage appears at its output, opening the charging switch 2. Through the open switch 2 and the diode 6 positive charge storage capacitor 4 flows onto the power rail

n "t

This process continues.

throughout the whole front

0

five

Yu

five

thirty

five

input pulse. When the charge growth at the input of the device stops, switch 2 closes and the remaining charge during the falling edge of the pulse is distributed between the signal source and the storage capacitor 4. Thus, at the end of the pulse, there is a negative charge on the storage capacitor 4, equal to the maximum value of the input pulse. This charge acts on the non-inverting input of amplifier 1, as a result of which a negative voltage is generated at its output, which through diode 7 creates at the device output a voltage equal to the voltage on the storage capacitor 4. The subsequent pulse will change the output voltage of the detector, if the amplitude of the subsequent impulse exceeds the amplitude of the n-rammer, a signal is generated at the additional output of the device, the duration of which is equal to the duration of the 4T front of the transformed impulse. The result is read at the end of the pulse or serica of the pulses. After reading, the reset switch 8 closes and the device is again ready to register the amplitude of the next pulse. If the charge of the transformed impulse is equal to cj, then the output voltage of the device

C

twt

Cn + C4

where C; - the capacity of the storage capacitor 4; Cp - the capacity of the signal source

(piezoelectric converter).

Dp increasing the storage time, the result of the conversion, the capacitor 9 and the switch 10 are inserted into the device (Fig. 2). During conversion, the device operates in the same way. At the moment of reading, the switch 10 closes and the charge of the piezoelectric transducer becomes equal to zero, thereby eliminating the effect of transducer leakage on the measurement result.

Claims (1)

1. Peak detector containing operational amplifier, charge the switch, the control input of which is connected to the output of the operational amplifier, the first output is with the power bus, and the second through the first resistor with a common bus and the first capacitor memory plate, the first electrode of the first diode is connected to the second output of the charging switch, and the second electrode - with the second plate of the safety capacitor and the non-inverted input of the operational amplifier, the inverting input of which is connected to the first output of the second resistor, the second electrode of the second diode and the tail of the device Ba, the first the electrode of the second diode is connected to the output of the operating an amplifier, characterized in that, in order to increase the accuracy, the second terminal of the second resistor is connected to the common bus, and the input of the device is connected to the second plate of the storage capacitor. 2, the Peak Detector of claim 1, wherein T is identified as being an additional capacitor and a switch were introduced, the first plate of the additional capacitor connected to the device input, and the second plate to the second plate of the storage capacitor, the first output of the additional switch connected to the device input, and the second output to the common bus.