SU1372617A1 - Probability a-d converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in specialized computing machines, computing and telemetry. The aim of the invention is to improve the accuracy of the conversion. The goal is achieved due to the fact that a device containing a 1 random number generator, a digital-to-analog converter 2, a block of 3 subtraction elements, a block of 5 comparators, a block of 6 anti-coincidence elements, an encoder 7, a block 4 of the conversion result correction is inserted, containing a summation element 12, a comparator 13 and two anti-coincidence elements 14 and 15. The random number generator 1 has a triangular distribution of random numbers, while the digital-to-analog converter 2 has twice the output voltage range, which ensures that the expectation and variance of quantization errors are independent of the distribution law of the input analog signal. 1 il. (L

Description

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The invention relates to digital computing and control technology, is designed to convert analog electrical signals into digital form and can be used in control computers, computing technology and telemetry.

The purpose of the invention is to improve the accuracy by ensuring the independence of the expectation value and the variance of quantization errors on the distribution law of the input analog signal.

The drawing shows a block diagram of a probabilistic analog-to-digital converter.

The device contains a generator of triangularly distributed random numbers, a digital-to-analog converter 2 (D / A converter), a block of 3 subtraction elements, a block A of the conversion result correction, a block of 5 comparators, a block of 6 anti-coincidence elements (EAS), an encoder 7, a clock 8 and an input 9, a bus, a bus 10 of reference voltages and an output bus 11. The conversion result adjustment unit 4 comprises a summation element 12, a comparator 13, a first 14 and a second 15 anti-coincidence elements.

Analog-to-digital converter works as follows.

The input bus 9 receives the input signal U (t), which must be digitized. Each subtracting element of block 3 reduces this input signal by its reference level U; and forms a differential analog signal

au, U (t) - and, where i 1, 2 ,. .., m which is fed to the second input of the corresponding comparator of block 5. Neighboring reference voltage levels differ by a constant sampling MJ. Summing element 12 forms an additional sum signal.

AUo- U (t) -t- UU U (t) -t- U, necessary to ensure the correction of the result of rounding of small voltages and which is fed to the second input of the comparator 13. To the first inputs of all the comparators of the unit 5 and the comparator 13 with the DAC i A random analog voltage U, distributed according to a triangular law in the range (0.2iU), is supplied discretely.

yu 15

20 25 ZO

Q

0

five

the clock pulse and constant during the digitization cycle.

This random voltage is generated by the generator 1 of the random numbers GS4 and DAC 2 distributed according to a triangular law after the next clock pulse triggering the RNG is received on the clock bus 8. Comparators compare this random voltage Up and the difference analog signal uU ;. At the outputs of the comparators, logical 1 is generated, if, and logical O at the inverse ratio.

Since the comparison of the differences MJ; produced with a random value varying in the range of 0.2uU and having triangular distribution laws, then simultaneously with the comparison and the digitization of the input signal that occurs at that, i.e. obtaining at the outputs of the comparators of a joint unitary code, probabilistic rounding of the input analog voltage is carried out, as a result of which the expectation and variance of quantization errors are independent of the distribution law of the input analog signal. The signals from the outputs of the comparators are fed to the EAS unit 6 and elements 14 and 15, which at the output produce a logical 1 only if there are opposite logical signals (O and 1) on the two inputs.

Thus, logical 1 occurs only on one EAS of block 6 or element 14 or 15, which is located at the transition boundary of signals from 1 to O at the outputs of block 5 of the comparator and comparator 13, i.e. on the one below which the comparators are typed 1, and above the logical ones O. On the output of the anti-matches of block 6 and elements 14 and 15, the encoder 7 generates an output n-bit code that is issued to the bus 11.

Compared with the known converter, the proposed method ensures the independence of the expectation and variance of quantization errors from the distribution law of the quantized signal, which increases the accuracy of the calculations.

We prove the existence of this property. Designate di quantizing discrete ADC. Likelihood density distribution

triangular in the interval from O to 2 or random voltage Ujr, with which the differences uU are compared; U (t) - U; for each reference level U ;, determined by

Oh, at 2uU;

one

W (Uu)

(iut (2li - U), come i

(

ABOUT,

at

-00 .c and

about 0.

(one)

at - 1X - up

The quantized signal U (t) is represented as V juU + and, where, j 0,1 ..., O and L and. Then, the result of preliminary rounding and further digitization can be presented as follows: Y JAU + y, where y is 1;

i 0,1,2 and is a correction for probability quantization, a multiple of U.

Since the rounding error is equal, the case of j 0, i.e. , Y y, 0.

To provide a uniform law of rounding of the input analog signal over the entire range, including small signals within the first quantization discrete O U: AU, the ADC uses a low voltage digitizing result adjustment circuit similar to the analysis chains for each reference voltage level in the ADC and containing the summation element 12, the comparator 13 and the two elements 14 and 15, the element 12, together with the positive reference level and whether forms a total signal

lo u (t) - (-U) u (t) + l. and

 u (t) + and

2

(2)

which is used as a minor difference signal and fed to the first comparator of block 5.

The second comparator of block 5 is supplied with a difference signal from the first subtraction element of block 3:

whether, D (t; - and, u (t) - O u (t).

(3)

All comparators, including these two comparators, compare their differential analogue

signal iU ;, i 1,2, ..., mco with a random voltage U and overlap the logical O in the case

with ; about

 .

15

20

25

thirty

35

40

jO

whether; and.

(four)

45

j; t and

and logical 1 with the inverse relationship.

In the case under consideration, on all the comparators of block 5, except for the first two, the logic ga- ges O at any random voltage Ue € (0.2 & U), since relation (4) is always fulfilled for them. At the outputs of the first and second comparators of block 5, the values of logical signals depend on the random voltage Ut, and the following combinations of the output signals of these comparators are possible: 00, 10, 11, which corresponds to corrections when rounding O, Li, 2, to determine the mathematical expectation and the variances Gy of rounding errors find the probability of forming these corrections P (0), P (1), P (2).

A zero correction O is generated in the ADC at the same time appearing at the outputs of the first and second comparators of block 5 logical O, which is fulfilled under the condition U (for the second comparator) and U "whether: Up (for the first comparator).

The probability of occurrence of the zero correction is equal to the probability of fulfilling the lower condition and is determined by the suppression

2bU5 U

p (o) I w (Uf) dUu j - (AU .U iUjo bU

- U) dU

The correction at 2iU corresponds to the appearance at the outputs of both logical comparators 1. The probability of forming the correction at 2AU is equal to the probability of fulfilling the condition

and and

R

(6)

and is determined from the following expression:

P (2) I W (U) dU -blVd

(7)

In other cases, a rounding correction is generated when logical 1 is generated at the first comparator and logical O at the second comparator. The probability of occurrence of such a correction rounding when digitizing is equal to

Р (1) 1 - Р (0) - Р (2) 1 - - | -jx

,, (di-i) -.U ..

(eight)

The expectation m. And the variance G and the roundness approximation for the found probabilities are determined as follows:

2

m - (i-uU - U) (.) (-U) X

one

X - and) + (& U - and)

L 2i

- ..

X (uU - and) - + (2uU - U) X

 W Y

L

Gl (i uU - U) 2.p (i) - m

yu1

four

Thus, the expectation m and var (and G rounding errors when digitizing in the proposed probabilistic ADC are equal to the corresponding uu "

but -V- and -t- and does not depend on the law

2 c

distribution of quantized analog voltage U (t).

Independence of probabilistic characteristics (expectation and variance) from the input signal eliminates uncontrollable loss of accuracy and makes it possible to compensate for systematic errors in the calculations, which leads to an increase in the accuracy of calculations or to a decrease in the requirement for high ADC.

Claims (1)

Invention Formula Vertical analog-to-digital converter containing block  ABOUT five 0 five 0 0 five elements of the subtraction, the first input of which is an input bus, the second group of inputs of which is a bus of uniformly increasing reference levels, a comparators unit, the first input of which is connected to the output of a digital-analog converter, the inputs of which are connected to the corresponding outputs of a random number generator, whose input is bus clock pulses, the outputs of the unit of subtraction units are connected to the corresponding second inputs of the comparators block, the outputs of which are connected to the corresponding inputs of the block anti-coincidence elements whose outputs are connected to the corresponding first inputs of the encoder, whose outputs are an output bus, characterized in that, in order to improve the accuracy, a conversion result correction unit is introduced, performed on the summation element, comparator and two anti-coincidence elements, the outputs of which are connected to the corresponding second inputs of the encoder; the first input of the first anti-matching element is a bus of the level of the logical unit; the second input of the first anti-matching element of the volume Inna with the first input of the second anti-coincidence element and connected to the comparator output, the second input of the second anti-coincidence element is connected to the first output of the comparators block, the first input of the comparator is connected to the output of the digital-analog converter, and the second input to the output of the summation element, the first input of which is connected to the input bus device, and the second is combined with the corresponding input of the second group of inputs of the block of elements of the subtraction, while the random number generator has a triangular distribution law uchaynnyh numbers.