SU1372273A1 - Time interval meter - Google Patents

Abstract

The invention relates to the field of measurement technology and can be used in automated systems. The purpose of the invention, the increase in measurement accuracy, is achieved by eliminating external interference. The meter contains integrators 1-3, Formers 4 and 5, amplitude

Description

selector 6, element AND-NOT 12, element OR-NOT 17, group of elements AND 20.1-20.p, triggers 7, 8, 15, 16, 19, 22 and 23, elements 9, 13 and 24 delay, counter 25, elements AND 10, 18, 26, 27 and 32, elements OR 11, 14, 21 and 28, elements NOT 29 and 33, elements AND-OR 30 and 31, registers 34 and 35 shift137

ha, generator 36, frequency divider 37, pulse distributor 38, input 39 and output 40 and 41 tires. The time interval meter ensures high reliability of operation in conditions of severe electromagnetic environment. 2 Il.

one

The invention relates to a measuring technique and can be used in automated measuring circuits.

The purpose of the invention is to increase the reliability of measurements by eliminating external interference.

Figure 1 presents the block diagram of the meter time intervals; figure 2 - timing charts of the meter.

The time interval meter contains integrators 1-3, shapers 4 and 5, amplitude selector 6, triggers 7 and 8, delay element 9, elements AND 10, OR 11 and AND-NOT 12, delay element 13, element OR 14, triggers 15 and 16, elements OR-NOT 17 and AND 18, trigger 19, a group of n elements AND 20.1-20.P, element OR 21, triggers 22 and 23, element 24 delay, counter 25, elements And 26 and 27, OR 28, NOT 29, ICSHY 30 and 31, And 32 and NOT 33, shift registers 34 and 35, generator 36, frequency divider 37, distributor 38 pulses, input 39, first 40 and second 41 output buses.

The input bus 39 through the integrator 1 is connected to the input of the imaging device 4, the output of which is connected to the inputs of the element AND NOT 12 and the delay element 9 directly and through the serially connected integrators 2 and 3, the amplitude selector 6 and the driver 5 to the C input of the trigger 7 and R -BXO- trigger 22, the first input of the element OR 11 and the second input of the element OR 14. The output of the trigger 7 is connected to the D-input of the trigger 8, the direct output of which is connected to the R-input of the trigger 7 and the second input of the element And 10, and

the inverse output of the trigger 8 is connected to the input of the element AND NOT 12, the output of which through the delay element 13 is connected to the C-input of the trigger 8.

The output of delay element 9 is connected to the input of element 10, the output of which is connected to the C input of trigger 15, the direct output of which is connected to the first input of element OR NOT 17 by one of the inputs of element 18 and the inverse output of trigger 15 is connected to C The trigger input 16, the direct output of which is connected to the second input of the OR-17, and its inverse output is connected to the C-inputs of the trigger 19 and 22 and the input of the element And 18, the output of which is connected to the C-input of the counter 25.

The output of the element OR 11 is connected to the R-input of the trigger 8, the output of the element OR 14 is connected to the R-inputs of the trigger 15 and 16, the output of the element OR-NOT 17 is connected to the D-input of the trigger 19, the output of which is connected to the D-input of the trigger 23, the output of which is connected to the first inputs of the elements AND 27 and 32. The outputs of the elements AND 20.1-20.P are connected to the inputs of the element OR 21, the output of which is connected to the first input of the element AND 26, the output of which is connected to the combined inputs of the elements AND-OR 30 and 31, the outputs of which are connected respectively to the information inputs of the shift registers 34 and 35, in The outputs are associated with the third steps of the AND-OR elements 30 and 31 and the output buses 40 and 41, respectively.

Direct output trigger 22 is connected to the second input element And 27, and its inverse output is connected to the second input element And 32, the outputs of the counter 25 are connected to the second inputs n elements And 20.1-20, p, the output element And 27 is connected to the second input element OR 28, the input element NOT 29 and the second input element AND-OR 30. The output element OR 28 is connected to the lane. the input of the element OR 14, the second input of the element AND 26, the R input of the trigger 19, directly and through the delay element 24, with the R input of the counter 25.

The output of the element NOT 29 is connected to the second input of the element AND-OR 30, the output of the element AND 32 is connected to the first (with the input of the element AND-OR 31, the inputs of the elements RSII 11 and 28, the input of the element 33, the output of which is connected to the second input of the element AND -OR 31. The generator output 36 is connected to the first 20 input of the element I 18 and the input of the frequency divider 37, the output of which is connected to the clock inputs of the shift registers 34 and 35 and the distributor 38 pulses, the first output of which is connected by 25 yen to the C input of the trigger 23 and n bit outputs are connected to the first inputs of the corresponding lean element. And in 20.1-20.p.

The meter works as follows.

Information about the measured value is output from the sensitive element (SE) (not shown) to the input bus 39 of the meter in the form of a grid of signals (Fig. 2a). At the same time, the first signal of a longer duration is a sync pulse determining the measurement cycle, two packs of four pulses with a duration of 5– Q 10 times smaller than the duration of the clock pulse represent information signals, the pulses between the sync pulse and the first burst of information pulses and between the bursts, the formation pulse pulses are interference signals on the communication line between the sensing element and the input bus 39 of the meter.

The signals from the input bus 39 arrive at shaper 4 through integrator 1, with the result that signals formed in amplitude and duration that do not contain interference signals (fig.2b) are formed at the output of shaper 4.

From the output of the imager 4 signals are fed to the input of the amplitude selec Q

s 0 5

about

Q with

0

five

torus 6 (Fig. 2b), passing through integrators 3 and 2. In the amplitude selector 6, the sync pulse of information pulses is separated. The introduction of two integrators 2 and 3 provides a more efficient selection of the sync pulse, the formation of which is carried out by the imaging unit 5 (Figure 2d). The sync pulse from the output of the imaging unit 5 translates the trigger 7 into state 1 (FIG. 2d), and the triggers 8, 15, 16, and 22 into the state O. Signals from the output of the imaging generator 4, having passed through the delay element 9, enter the input of the element I 10, the second input of which receives a signal from the direct output of the trigger B, which switches to state 1 (FIG. 2e) at the end of the clock pulse passed to the trigger input 8 through the AND-NE element 12 and the delay element 13. At the same time, at the output of the element 10, a signal appears (fig. 2g) also at the end of the sync pulse. The choice of the delay value of the delay element 9 should provide compensation for the delay of the clock pulse as it passes through the integrators 2 and 3, the amplitude selector 6, the driver 5, the element OR 11, and the trigger 8.

The proposed meter is intended to measure in one cycle time intervals between two information pulses of each pack of four pulses, depending on the measurement mode chosen by the operator. The following description of the operation of the meter considers the mode in which time intervals T | are measured in each burst. between the first and second pulses. The elements associated with the selection of the measurement mode are not shown.

The signals from the output of the element 10 are fed to the input of the trigger 15, which, together with the trigger 16, selects pulses between which time intervals are measured. In this case, at their outputs, signals are generated (Fig. 2i, k) arriving at the inputs of the And 18 element, to the first input of which quantization pulses are received from the generator 36. The pulse bursts from the output of the And 18 element (Fig.2l) are proportional to the measured time intervals, arrive at the input of the counter 25.

Information from the outputs of the counter 25 about the size of the measured time intervals is retrieved by polling signals generated by triggers 19, 22 and 23, elements AND 27 and 32, OR-NOT 17, OR 28 and delay element 2A. The flip-flop 19 switches to state 1 at the end of any bundle of information signals and excites the input of the D-flip-flop 23, which is triggered by synchronizing pulses 1 and from the output of the distributor 38. Thus, polling signals are generated at the flip-flop 23, Fig recorded in the generator pulses 36. The binding is due to the fact that the information on the measured time intervals in the meter is represented by a binary sequential stake.

The trigger 22 performs the polling signal distributions to record information in time slots either in the shift register 34 or in the shift register 35.

The interrogation signal of the second measured interval from the output of the element 32 (fig.2n) is fed to the K-pass of trt ggera 8 (fig.2o), translating it to oh I thus removing signal 1 from the input of the element AND 10. At the same time, the meter is prepared for the next measurement cycle, the information signal signal and the output signal of the element And 10 closing (FIG. 2e, g) before the next clock pulse, thereby preventing the signal from penetrating interference into the measuring part of the device.

Claims (1)

Invention Formula A time meter, containing a generator, the output of which is connected to the first input of the first element I and the input for the frequency, two shift registers and a pulse distributor, the first output of which is connected to the C input of the first trigger, and the remaining n outputs are connected to the first inputs of the corresponding elements And, the second inputs of which are connected to the corresponding outputs of the counter, and their outputs are connected to the inputs of the first element OR, the output of which is connected to the first input of the second element AND, three elements behind 37227 6 holder, two elements are NOT, the direct output of the first trigger is connected to the first inputs of the third and fourth elements AND, the output of the last is connected to the first input of the second element OR, the output of which through the first delay element is connected to the R input of the counter, the fifth element And, the third and fourth elements OR, the second, third, the fourth and fifth triggers, characterized in that, in order to increase the reliability of measurements, two AND-OR elements are introduced into it, 15th sixth and seventh triggers, AND-NOT element, OR-NOT element, two pulse drivers, three integrators and an amplitude selector, the meter input bus through a sequential 20 but connected first first integrator and a pulse shaper connected to the second integrator and the first input of the element AND-NOT directly and through the second delay element 25 to the first input of the fifth AND element, whose input is connected to the C input of the second trigger, the direct output of which is connected to the first input of the OR-IE element and to the second input of the first elec ment, the third input of which is connected to the inverse output of the third trigger frequency and to the C inputs of the fourth and fifth triggers, and the output to the C input of the counter, the inverse output of the second at the trigger, it is connected to the C input of the third trigger, the direct output of which is connected to the second input of the element ORNI, the output of which is connected to the D-BXO- house of the fourth trigger, the direct output of which is connected to the D input of the first trigger, and R-input is connected to the output of the second element OR, the second input of the second element AND, the first input of the third element OR, the output 45 of which is connected to the R-inputs of the second and third triggers, and the second input to the R-input of the fifth trigger, the first ry input of the fourth element OR, the output of the pulse former and 50 C-input of the sixth trigger, the direct output of which is connected to the D-input of the seventh trigger, the direct output of which is connected to the R-input of the sixth trigger and the second input of the fifth element AND, the R-input of the seventh trigger is connected to the output of the fourth element OR , the second input of which is connected to the output of the fourth element I and to the first input of the first element This AND-OR directly and through the first element is NOT to the second input of the first element AND-OR, the third input of which is connected to the output of the first shift register and the first output bus of the meter, the output of the third element AND is connected to the second input of the second element OR and to the first input The second element is AND-OR directly and to its second input through the second element NOT, the third input of the second element AND-OR is connected to the output of the second shift register and to the second output bus of the meter, the fourth inputs of the first and second elements are AND-OR combined s and connected to the output of the second AND gate, and their outputs are connected to data inputs eight the first and second shift registers respectively, the clock inputs of which are connected to the output of the frequency divider and the input of the pulse distributor, the output of the second integrator is a series-connected third integrator and the amplitude selector connected to the input of the second pulse forwarder, the inverse output of the seventh trigger is connected to the second input of the AND element -NOT, the output of which through the third delay element is connected to the C input of the seventh trigger, the direct and inverse outputs of the fifth trigger are connected to the second inputs of the corresponding naturally the third and fourth elements I. FIG. 2