SU1368918A1 - Read amplifier - Google Patents

Abstract

The invention relates to computing and can be applied to create read amplifiers for memory devices. The aim of the invention is to increase the speed of the read amplifier. The Sshitsany amplifier contains emitter repeaters on transistors 7, 8 and resistors 9 and 10, a differential cascade on transistors 11 and 12, a two-emitter limiting transistor 13, first and second generators 18 and 19 of current transistors, resistors 14-16, power supply bus 5, input 17 reference stress. The use of the limiting transistor 13 and the reference voltage at the input 17 results in a lowering of the operating voltage drop across the bases of the transistors 11 and 12 as compared to the voltage drops across the bases of the transistors 7 and 8, as a result of which the performance of the amplifier is increased. 1 il. § (L

Description

The invention relates to computing technology and can be applied to create read amplifiers for memory devices.

The aim of the invention is to increase the speed of the read amplifier.

The drawing shows a schematic diagram of the proposed reading amplifier.

The diagram shows the first and second 2 information inputs, the first 3 and second 4 outputs of the read amplifier, power supply bus 5 and bus 6 of zero potential.

The read amplifier contains the first 7 and second 8 transistors of the emitter followers, the first 9 and second 10 resistors, the first 11 and second 12 transistors of the differential stage, the two emitter limiting transistor 13, the third to fifth resistors 14-16. .

In the drawing, the input 17 of the reference voltage of the amplifier is indicated. The sense amplifier also contains transistors 18 and 19 of the first and second current generators.

I increase the speed of the amplifier.

To ensure this, the value of the reference voltage at the output 17 must be selected in accordance with the condition

and,.

 Zch., And „„

Uc + and

v5

and, 8 de Uf is the voltage at the base of transistor 11 (or 12) with logical 1 at input 1 (or 2);

the voltage drop across the base-emitter junction of the transistor 13;

 - temperature potential;

Ujf, is the reference voltage on the input 17;

Vf- voltage at the base of transistor 12 (or 11) with a logical O at input 2 (or 1) with respect to the bus 6.

formula of the invention reading amplifier containing

The read amplifier operates barely the first and second emitter in a repeated manner.

The signals at inputs 1 and 2 are transmitted to the bases of transistors 11 and 12, respectively, through transistors 7 and 8 and resistors 9 and 10 as current flows through them from transistors 18 and 19, to the bases of which the reference voltage is supplied from resistor 16.

Transistors 11 and 12 and resistors 14 and 15 form a differential cascade, with the signal at outputs 3 and 4 being removed from resistors 14 and 15, respectively.

When a high level signal arrives at input 1, and transistor 11 opens at input 2 at low level, transistor 12 closes, low level is output 3, and high level is output 4. When the opposite information arrives, the state of transistors 11 and 12 and outputs 3 and 4 change accordingly.

The reference voltage at input 17 and transistor 13 reduce the operating voltage drop across the bases of transistors 11 and 12 as compared to the voltage drops at inputs 1 and 2 and the capacitors on the transistors, the emitters of which are connected to the first terminals of the first and second resistors , differential cascade on transistors, first and second current generators on transistors and third to fifth resistors, with the collectors of transistors of the first and second emitter followers and the first conclusions of the third and

fourth resistors are connected to

other power, the bases of the transistors of the first and second emitter followers are information inputs of the device, the second inputs of the first and second resistors are connected respectively to the bases of the first and second transistors of the differential stage, the collectors of which are connected respectively to the second terminals of the third and fourth resistors and are respectively the first and the second outputs of the amplifier, the emitters of the first and second transistors of the differential cascade are connected to the first output of the fifth transistor and ba s of transistors of the first and second current generators, collectors of which are connected respectively to the bases of the first and second

 13689184

differential cass transistors, the base of which is

kada, emitters of transistors by the primary input of the reference voltage of the amplifier,

and the second current generator and the second collector is connected to the power bus,

The output of the fifth resistor is connected with the spritch of the first and second emitters with a zero potential potential gap, the current transistor is connected with the fact that, for the purpose, respectively, of the base of the first and

increase the speed, in it in the base of the second transistors differential

den two-emitter restrictive cascade.

Claims (1)

Claim A read amplifier containing the first and second emitter repeaters on transistors, the emitters of which are connected to the first terminals of the first and second resistors, the differential cascade on the transistors, the first and second current generators on the transistors, and the third to fifth resistors, and the collectors of the transistors of the first and the second emitter followers and the first conclusions of the third and fourth resistors are connected to the power bus, the base of the transistors of the first and second emitter. repeaters are information inputs of the device, the second terminals of the first and second resistors are connected respectively to the bases of the first and second transistors of the differential stage, the collectors of which are connected respectively to the second terminals of the third and fourth resistors and are respectively the first and second outputs of the amplifier, the emitters of the first and second transistors of the differential stage connected to the first output of the fifth transistor and the bases of the transistors of the first and second current generators, collectors They are connected respectively to the bases of the first and second transistors of the differential stage, the emitters of the transistors of the first and second current generators and the second output of the fifth resistor are connected to the zero potential bus, characterized in that, in order to improve performance, a two-emitter limit transistor is introduced into it, the base of which is the input of the reference voltage of the amplifier, and the collector is connected to the power bus, and the first and second emitters of the limiting transistor are connected respectively to the base th and the base of the second transistor differential stage.