SU1367140A1 - Shaper of pulses of electrodynamic analyzer - Google Patents

Abstract

The invention is intended for use in energy analyzers of multi-charge ions in which the formation of the voltage U (t) U, O t Cu U (t) and 51, t i -D-, where Uo is the voltage pulse amplitude, s - time of flight of ions from the place of formation of a plasma bunch to the detector. In this case, in an electrostatic field, ions are separated by charge, regardless of energy. The aim of the invention is to improve the accuracy of the formation of pulses of an electrodynamic analyzer. The device contains analog switches 1 and 2, linear integration unit 3, dual integrable unit 4, delay unit 5, key control unit, programmable voltage source 7, analog multiplier 8, adder 9, voltage division 10, sources 11 and 12 of the reference voltage, the comparator 13, blocks 14 and 15 of the installation of initial conditions, input 16, 17 and 18 and output 19 tires. The device provides the ability to control the amount of delay, slope of the generated pulses and the initial voltage level. 1 il. with (L

Description

with

ABOUT)

The invention relates to a pulse technique and is intended for use in energy analyzers of multi-charge ions, in which the formation of a voltage of the form is necessary.

Wow.

about t

four

 about

ts cr

(one)

where io is the voltage pulse amplitude; T is the time of flight of ions from the place where the plasma bunch was formed to the detector. In this case, in an electrostatic field, ions are separated by charge, regardless of energy. I x

The purpose of the invention is to test the accuracy of the formation of pulses of an electrodynamic analyzer.

The drawing shows a block diagram of the device.

The former contains the first and second analog switches 1 and 2, the linear integration unit 3, the double integration unit A, the delay unit 5, the key management unit 6, the programmable voltage source 7, the analog multiplier. 8, d -; - mmator .9, voltage division unit 10, first and second sources 11 and 12 of the reference voltage, comparator 13, first and second blocks 14 and 15 of the initial conditions, first, second and third input buses 16i 17 and 18, the output bus 19.

Linear integration unit 3 is a reset integrator, dual unit 4, integration can be implemented as a serial connection of two reset integrators. The delay unit 5 generates a pulse at its output with a delay b relative to the pulse on the first input bus 16, and the value / can be regulated by a code on the second input bus 17. Block 6 can be executed in the form of an R-S flip-flop.

In the initial state, the analog switches 1 and 2 are open, the signal from the output of block 6 through blocks 14 and 15 closes the keys in blocks 3 and 4, and the voltages U and UH are set at the outputs of the latter, which can be set, for example, feeding appropriate levels of voltage to non-inverting

The inputs of the operational amplifiers included in the integrators are reset in blocks .3 and 4.

The start pulse arrives at the first input of block 5, from the output of which the pulse delayed by time ta arrives at block 6, which converts both analog switches 1 and 2 to a closed state. At the same time, through the analog key 1 to the first input of the linear integration unit 3, the current generated by the programmable power source 7 flows. The magnitude of the voltage E, from the unit 7, is set on its input by a binary code from the mainline computer. As a programmable source 7, a digital-to-analog converter can be used. Through the analog switch 2 to the input of the double integration unit 4, the current generated by the voltage at the output of the analog multiplier 8 with the combined inputs connected to the programmable source 7 flows. Therefore, the voltage at the output of the analog 8 is

multiplier AND is.

The voltage at the output of the linear integration unit 3 varies according to the law

five

U, (t) UH- +

t-t

(- / - v H, r -t

and the voltage at the output of block 4 of the integration

(t-)

(2) double

: (t) U, -b

H

to,

E.

tif

(3)

where r, blocks

7- constant times

four.

Select the values of the constant time5

G, - (:, and U, (t)

meni t

The voltages Uj (t) and) are fed to the inputs of the adder 9, at the output of which, in accordance with the voltages (2) and (3), a voltage is generated

Ujt)

U (t) 2U, (t) + U2 (t) n (and,

Uh

F, f

tsf

W

five

where and.

2U "+ U

Mi

When the voltage value is u

u, (t.)

exceeds

then formed by the source 12 of the reference voltage, the comparator 13 is triggered, which through block 6 will transfer the analog switches 1 and 2 to the open state. i

Thus, the duration of pulsed pulses is

/ 7

Chmp -4irj.

at time t 0 +, block 3 is set. in the initial condition and in the first block 14, and block 4 in the initial condition 1)) ;, the second block 15.

Voltage 1) 5 (1) is applied to the second input of the block 10, and the source P of the reference voltage Ufp is connected to the first input of the block 10. A voltage is generated on the output bus 19 of the device.

Ujt)

.Un-uh Ku

(and

..,)

tijr

(6)

 S

where Ku is the scale factor of the dividing unit of two voltages corresponding to a specific switching circuit.

Comparison of expressions (1) and (6) allows you to determine the parameters of the pulses of the generator

(7)

(eight)

-one

Compared with the known device, this device has a higher accuracy, since it multiplies the constant voltage, rather than changing, as in the known device. In addition, it is possible to control the magnitude of the delay, the steepness of the decay of the generated pulses, and the initial level of voltage.

B

formula of the image

Electrodynamic analyzer pulse generator comprising a delay unit, programmable voltage source, linear integration unit, first and second analog keys, key control unit, analog multiplier, unit

one

367140 4

dividing the voltage, the comparator, the first and second sources of the reference voltage, the first and second blocks of setting the initial conditions, the first and second inputs of the delay unit are connected to the first and second input buses, respectively, and the output is connected to the first input of the control unit - 10 NIN keys on the inputs of the first and second blocks for setting the initial conditions, the key of the key control block is connected to the control inputs of the first and second analog keys, 15 OUTPUT; the programmable voltage source is connected to the information input of the first analog switch, and the input is connected to the third input bus, the output of the first analog switch 20 is connected to the first input of the linear integrator, the first input of the two voltage divider is connected to the output of the first voltage source, the first the input of the comparator 25 is connected to the output of the second source of the reference voltage, and the output is connected to the second input of the key management unit; the output of the first installation unit of the initial voltage is connected to the second input ohm 30 linear integration unit, the output of the dividing unit of the two voltages is connected to the output bus, characterized in that, in order to improve the pulse shaping, a double integration unit and an adder are introduced into it, the first and second inputs of the analog multiplier connected to the output of the programmable source, and the output is connected to the information input of an analog switch, the output of which is connected to the first input of the double integration unit, the second input of which is connected to the output

45 of the second unit for setting the initial conditions, the first input of the adder is connected to the output of the linear integration unit, the second input is connected to the output of the double integration unit,

50 and the output - with the second input of the comparator and the second input of the voltage dividing unit.

36

Claims (1)

Claim An electrodynamic analyzer pulse generator comprising a delay unit, a programmable voltage source, a linear integration unit, first and second analog keys, a key control unit, an analog multiplier, the unit of which is connected to the first input of the double integration unit, the second input of which is connected to the output 45 of the second installation unit initial conditions, the first input of the adder is connected to the output of the linear integration unit, the second input to the output of the double integration unit, 50 and the output to the second input the comparator ode and the second input of the voltage division unit. VNIIIPI Order 6851/54 Circulation 928 ______ Subscription Native polygr. ave, city of Uzhhorod, st. Project, 4