SU1362271A1 - Digital-to analog automatic tachometer - Google Patents

Abstract

This invention relates to a measurement technique. The purpose of the invention is to reduce the measurement error. Depending on the duration of the measured interval, the bits of counter 8 are filled. The high level of the signal from the high bit output of register 9 permits the passage of pulses of the reference frequency through the AND 7 circuit to the register input of the register 9. Each pulse from the output of the AND 7 circuit shifts information in register 9. After the shift operation, for any duration of the measured interval, in the higher bits of register 9, there is information that is fed to the multiplying digital-to-analog converter 16 in the form of a binary to An ode containing n binary bits, where n the width of a digital-to-analog converter 16. 1 Il. (L

Description

 1. 13

11, the clause referred to the Fiin i impeller technique and the automaton {Ky and can b (, rb is used for precision; - measurement of the rotation frequency,

Uej7b sentences - reduction of measurement accuracy.

The tachometer block diagram is shown in the drawing and contains a Tachometer sensor 1, a pulse shaper 2, a trigger 3, a shaper of rewriting and resetting pulses 4, a generator of exemplary frequency 5, two AND 6, and an r-second dual counter 8 , shift register 9, digital-to-analog converter 10, analog indicator 11, additional binary counter 12, decoder 13 and digital indicator 14 “D / A converter” contains an operational amplifier 15, multiplying digital analog converter 16, resistor 17 and source obra tsovogo voltage 18.

one

The tachometer sensor 1 is connected via pulse forming pulses 2 to the counting input of the trigger 3, the direct output of which is connected to the input of the overwriting and resetting pulses 4 and one of the inputs of the circuit 6, and the output of the circuit 6 with the other inputs of the circuit 6 and 7 are connected to a generator of exemplary frequency 5, and the third input of circuit I 7 is connected with the inverse output of the last trigger of shift register 9, the parallel inputs of which are connected to the outputs of the main binary counter 8, and the higher bits of the output ); their entrances digital anaphora converter 16. The reset output of the paresayisi and reset 4 pulse mapper is connected to the reset input of the main counter 8, and the overwrite code is connected to the overwriting input of the register 9 and the reset input of the additional counter 12. The output of the first circuit And 6 is connected to the counting input of the main of the counter B, the outputs of the circuit 7 with the shift input of the register 9 and the counting input of the counter 12, the outputs of the counter 12 are connected to the inputs of the decoder 13, the outputs of which are connected to a digital indicator 14. The output of the operational amplifier 15 is connected DEN minutes indicator 11 and the multiplying digital to analog converter input 16, Zain communication output to the input of the operational amplifier 15, pod12

key black; h reistor 17 to the source of exemplary voltage 18.

An automatic tachometer is following in the image.

The tachometer sensor 1 associated with the shaft generates a sinusoidal signal whose frequency is proportional to the speed of rotation of the shaft and which is converted into square pulses by the driver 2 and fed to the counting input of the trigger 3. The switching frequency of the trigger is proportional to the input frequency F and, therefore, to the frequency shaft rotation. At the direct output of the trigger, a time interval is formed equal to one period of the input frequency F, during which the circuit 6 transmits pulses with a frequency f of the sample generator 5 to the counting input of the main counter 8. After the end of the time interval, the driver 4 generates shifted pulses which overwrites the contents of counter 8 into register 9 and resets counter 8, preparing it to measure the duration of the next-period input frequency. Simultaneously with the rewriting of the code, the additional binary counter 12 is reset, which prepares it for operation.

After the end of the measuring time interval, the trigger 3 is switched. At its inverse output a level appears that permits the passage of the pulses of the reference oscillator 5 through the AND 7 circuit to the shift input-register 9.

Depending on the duration of the measured interval (period), the bits of the binary counter 8 are filled, i.e. at high rotational speed, the high bits of the counter remain in the zero state. In this case, the high level of the signal from the inverse output of the last high-order bit of the shift register 9 permits the passage of pulses of an exemplary frequency through the AND 7 circuit to the shift input of the register 9. Each pulse from the AND 7 output shifts the information in register 9 by one bit, which corresponds to a zoom in two times. The information is shifted to the register until the logical unit is higher than the previous one, then: the zero level from the bottom of this way prohibits further passage of pulses through the AND 7 circuit. The number of pulses passed through the AND 7 circuit is counted by an additional counter 12, is decoded by the decoder 13 and is indicated by a digital indicator 14 as a scale factor 2, where m is the number of chips passed through the AND 7 circuit and counted by counter 12, It is equal to the number of binary bits to which eh right information in the shift register 9.

Thus, after the shift operation for any duration of the interval being measured (the input frequency period), in the high bits of register 9, there is information which sends a multiplying digital-to-analog converter 16 in the form of a binary code N containing ti binary bits, where - digital-to-analog converter size.

Claims (1)

Invention Formula A digital-analogue automatic tachometer containing a series-connected tachometric sensor, a pulse shaper, a trigger, and a shaper of overwriting and resetting pulses connected to its direct output; connected in series base double counter, memory register, digital-analog conversion 0 5 0 5 about five gel with pcltcimi silt its output is ana-. A bare indicator, as well as an exemplary frequency generator, the reset output of the write and reset pulse shaper, is connected to the reset input of the main binary counter, and the overwrite output is connected to the register write input, which is different from In order to reduce the measurement error, it additionally introduces two AND circuits and an additional binary counter, a decoder and a digital indicator in series, and the memory register is made in the form of a shift register, the outputs of the higher bits of which are connected the digital-to-analog converter, and the low-order bits are left free, the two inputs of the first circuit AND are connected respectively to the direct output of the trigger and the generator of the reference frequency, and the output to the counting input of the main binary counter, the two inputs of the second circuit AND are connected respectively with an inverse trigger output and a generator of exemplary frequency, the third input is associated with the inverse output of the higher bit of the shift register, and the output is connected to the shift input of the shift register and the counting input of the additional double a counter with a reset input which is key to the overwriting output of the overwrite and reset pulse generator. / 2 J I- HEDGEHOG. .. t