SU1361546A1 - Computing device - Google Patents

Abstract

The invention relates to computing and can be applied to coordinate transformation in three-dimensional space. The aim of the invention is to simplify the device. The device contains a vector 1 rotation unit, registers 2-4, switches 5-7, adders-subtractors 8-10, a decoder 11, a counter 12, a control block 13. The device allows rotation around three axes in a three-dimensional coordinate system based on the Volder iterative algorithm. Unlike traditional variations of the Vulder algorithm in the device, the rotation is carried out with a constant step, which leads to a simplified structure of the control part of the device. 2 Il. / 50 16 o (l w oo o) ate 4 05 23 tlZ.i

Description

113

The invention relates to computational engineering and can be used to transform coordinates in three-dimensional space.

The purpose of the invention is to simplify the device by rotating the vector in constant increments.

Figure 1 shows the functional diagram of the device; Fig. 2 is a functional block diagram of the control unit.

The device contains a vector 1 rotation block, the first 2, second 3 and third 4 registers, the first 5, the second 6 and the third 7 switches, the first 8, the second 9 and the third IO of the North-West subtracter, the decoder 11, the counter 12, the control unit 13 , input 14 of the first argument, input 15 of the second argument, input 16 of the third argument, input 17 of the fourth argument, input 18 of the conversion type, group of clock inputs, 19, first information output 20, second information output 21, third information output 22, input 23 of signal the end of the turn, the first group of outputs .24 control unit laziness, the first output unit 25 zshravle

NIN, the second group of outputs 26 of the control unit.

The control unit contains the encoder 27, the pulse distributor 28, the trigger 29, the first 30, the second 31, and the third 32 elements I.

The device functions as follows.

The calculations in the device are carried out in accordance with the algorithms.

rotation around the x axis at an angle v;

(t 1l

2

-k

- l.,. 2 l Sch-2

-to

-to

-k

.v / 2 (1)

,

sign (f

0 at

 0 when

rotation around y axis

X

X2i-Vi;

5's

Yji + v -Y- ,, 1 (-1 1 AgX / j -2 6.4, 0.- Lb 2-S i 0,1,2 ... 0/2

Cho

X ,; Zj, Z, j 00

6 sign 0

ABOUT

at

at

rotation around the Z-axis at an angle:

YS; .. Xs, + L Uzg2-,

- f X

Y 3Ui - Yl Z jij., Zj,

; - - 2, i 0,1, 2 ... / 2-,

X ,; Yi-o y

i-c

(3)

thirty

1.2, IjO

g

 sign with E; f 0

e0 when

The rotation no to the algorithms (l) - (3), in contrast to the traditional varieties of the Wolder algorithm, is performed at all iterations i with a constant step L 2..

Before the start of calculations in registers 2-4 on inputs 14-16, it goes Y

X coordinates

Z p respectively, and in the counter 12 at the input 17 is the angle value. Before executing each of the transformations (1) - (3) at the input 18, a code of the type of transformation 5 is set, according to which unit 13 controls the switches 5-7 on the first output 25. The operation modes of the adders-subtractors 8-10 are carried out according to the signals at the second

Q group of outputs 26 of control unit 13 produced based on the sign of the angle and the code of the type of transformation in accordance with algorithms (1) - (3).

Calculations begin with the Work signal post-input signal at input 19, according to which unit 13 on the first group of outputs 24 receives information shift signals in registers 2-4. When performing conversion (1), the switch 5 is closed, the switch 6 connects the output of register 4 (Zj 2) to the input of the subtractor 9, and the co-switch 7 connects the output of the register 3 (Y; -2) to the input of the adder-10. (1 + 1) -th iteration coordinates X, Y-, Z, with the codes of registers 2-4 are fed to the inputs of adders-subtractors 8-10, respectively. Since the switch 5 is closed, the coordinate is rewritten through the adder-subtractor 8, remaining at all iterations unchanged. On the subtractor 8, a new value of the Y coordinate is calculated.

0

five

0

-.

5- Y ,,, Y ,. ,

and on the adder-subtractor 10 - new

coordinate value

ZH .; Z ;;

- Y

which are written to registers 3 and

4 respectively. At the end of each iteration i + l, the counting input of the counter 12. C of the control unit 13 receives a counting pulse, and the contents of the counter are reduced by one.

Counter 12 contains the reverse code of the angle V. The output at each iteration to its counting input signal +1 (with a weighting factor of 2) is equivalent to subtraction. When a corner is fully developed, the decoder 11 is triggered and, by its signal, the control unit 13 switches off the shear series on the bus 24. Calculations end. At the output 23 of the control unit 13, a conversion termination signal is set.

Transformations (2) and (3) are similarly performed.

Claims (1)

The control unit functions as follows. The conversion code is defined by a three-bit bus 18, each bit of which defines a certain type of conversion. These signals directly control switches 5-7. At the outputs of the encoder 27, control signals of subtractors 8-10 are generated. At the output of the encoder 27f, the operation mode of the adders is indicated, and the number indicates to which subtractor the current mode is referred to as the Third Element AND 32 in the first cycle, the iteration signal 19.2 turns on the trigger 29 and the second Element And 31 allows the shear out series on registers 2-4. In the first element 30, in the last iteration cycle, a signal is generated that arrives at the counting input of counter 12. After the angle has been fully processed, the signal from the decoder 11 zeroes trigger 29 and signal 23 of the end of rotation turns out. Invention Formula A computing device that contains a vector rotation block that contains three registers, three SSs of the subtractor and three switches and a control unit, the inputs of the first, second, and third arguments of the device are connected to the first information inputs of the first, second, and third registers, respectively; the inputs of which are connected to the codes of the first, second and third totalizers subtractors, respectively, the inputs of the first operands, the first, second and third subtractors totalizers connected to the outputs of ne R second, third and third registers, respectively, the inputs of the second operands and the first, second, third summators-subtractors are connected to the outputs of the first, second, and third switches, respectively; the clock and shift inputs of the first, second, and third registers are connected respectively to the first and second the outputs of the first group of the control unit, the first output of which is connected to the control inputs of the second, third and first switches, respectively, the first, second and third outputs of the second group of the control unit and connected with the control inputs of the adders-subtracters, the first to third outputs of the first, second and third adders-subtractors connected respectively to the first WTO the second information output device of the device, the second output of the control unit is the output signal of the device’s rotation end, the input of the conversion type and the group of clock inputs of the device are connected respectively to the same input and group of inputs of the control unit, in order to simplify the device by rotation of the vector with constant pitch, the device contains a counter and a decoder, with the math input, the counter is connected to the input of the fourth argument of the device, the counting input of the counter Connected to the third output of the control unit, the information outputs of the counter are connected to the inputs of the decoder, the outputs of which are connected to the input of the sign zero of the angle of the control unit, the input of the analysis of the sign of which is connected to the output of the higher bit of the counter, the output of the first register shifted by K to the lower ones bits (K - rotation constant) is connected to the first information input of the second and third switches, the output of the second register with a shift to K bits towards the lower bits is connected to the first information input One of the first and second information inputs of the third switch, the third register code with a shift of K bits toward the lower bits is connected to the second information inputs of the first and second switches. J9 Btn. 4 (1 /. Editor N. Tupitsa Compiled by S.Kulikov Tehred A. Kravchuk Proofreader N. Korol Order 6291/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 t w J7 74 .g