SU1345165A1 - Voltage stabilizer for supplying clock integrated circuit - Google Patents

Abstract

The invention relates to electronic time devices. The purpose of the invention is. reduced power consumption. The device contains negative 1 and common 2 busses of the primary power supply, reference p-channel transistor 3, p-channel transistor 4, resistors 5, 10 and 14, crystal oscillator 6, frequency divider 7, bus p-channel transistor 9, transistor -controller 11 load current, generator 12 of capacitive current, suppressor p-tap transistor 13 and. bus 15 power. The introduction of new ele. new connections between the elements of the device allows to reduce the level of energy loss, since reducing the supply voltage of the crystal oscillator 6 to a value less than the sum of the threshold voltages of the p-channel and 4 and p-channel 9 transistors, eliminates through-. Inverting amplifier current due to overcharging of input and output powers of capacitor total generator 12. 4 il. i (L 1 01 O5 SP

Description

The invention relates to electronic time devices and can be used to create autonomous watches in the form of an integrated circuit on complementary (mutually complementary) metal oxide semiconductor logic elements (on CMOS logic elements).

The aim of the invention is to reduce power consumption per hour CMOS integrated circuit.

FIG. 1 shows the electrical structure of the stabilizer; on

FIG. 2 - electric functional g of the resistor-controller 11 load current.

capacitive current generator circuit; in fig. 3 - electric functional circuit of the quartz oscillator; in fig. 4 - electrical functional frequency divider circuit.

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The first output of the crystal oscillator 6 is connected to the second input of the capacitor power generator 12, the first output of which is connected to the gate of the load p-channel transistor 4, the gate of the reference p-channel transistor 3 and through the first resistor 5 to the drain of the reference p-channel transistor 3 and to the gate of the reference p-channel transistor 13, connected by its source to the second output of the capacitive current generator 12 and through the third resistor 14 to its substrate and to the bus 15 of stabilized power. The stabilized power supply bus 15 is connected to the stabilized power input of the frequency divider 7, the second output of which is connected to the gate of the n-channel transistor 9, the drain of which is connected to the source of the n-channel transistor 13 connected to the drain of the load p-channel transistor 4, y the substrate and drain are connected to the common bus of the primary power source. The negative bus of the primary power supply is connected through the second resistor 10 to the source of the transistor-regulator 11 of the load current, to the source and substrate of the n-channel after-load transistor 9 and to the power input of the capacitive current generator 12, the first input of which is connected to the second output of the crystal oscillator 6,

The stabilizer contains (see Fig. 1) common and negative busses of the primary power source 1 and 2, the reference p-channel transistor 3, the load p-channel transistor 4, the first resistor 5, the crystal oscillator 6, the frequency divider 7, the output bus 8, p-channel after-load transistor 9, the second resistor 10, the transistor-regulator 11 of the load current, the capacitor current generator 12, the p-channel transistor 13, the third resistor 14 and the stabilized power supply bus 15.

Capacitive current generator 12 (FIG. 2) comprises a smoothing capacitor 16, first and second switching transistors 17 and 18, first and second switched capacitors 19 and 20, and third and fourth switching transistors 21 and 22,

The quartz generator 6 (FIG. 3) contains a p-channel transistor 23, a p-channel transistor 24, a feedback resistor 25, a crystal oscillator 26, an input capacitor 27 and an output capacitor 28.

Frequency divider 7 (FIG. 4) contains an inverter 29, a series circuit of loaded triggers 30-46, a capacitor 47, a resistor 48, a trigger 49, a transistor 50, a load resistor 51, a transistor 52 and a resistor 53, output 54.

The common bus of the primary power source 1 is connected to the source and the substrate of the reference p-channel transistor 3, to the common power inputs of a crystal oscillator 6 and a frequency divider | 7, the input of which is connected to

a first output of a quartz oscillator 6 connected by its power input to the bus 15 of stabilized power.

The output bus 8 is connected to the first output of the frequency divider 7, the primary power input of which is connected to the negative bus 2 of the primary power and the substrate of the transistor-regulator 11 of the load current connected to the drain of the reference p-channel transistor 13, whose source is connected to the drain transistor transistor controller 11 load current.

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The first output of the crystal oscillator 6 is connected to the second input of the capacitor power generator 12, the first output of which is connected to the gate of the load p-channel transistor 4, the gate of the reference p-channel transistor 3 and through the first resistor 5 to the drain of the reference p-channel transistor 3 and to the gate of the reference p-channel transistor 13, connected by its source to the second output of the capacitive current generator 12 and through the third resistor 14 to its substrate and to the bus 15 of stabilized power. The stabilized power supply bus 15 is connected to the stabilized power input of the frequency divider 7, the second output of which is connected to the gate of the n-channel transistor 9, the drain of which is connected to the source of the n-channel transistor 13 connected to the drain of the load p-channel transistor 4, y the substrate and drain are connected to the common bus of the primary power source. The negative bus of the primary power supply is connected through the second resistor 10 to the source of the transistor-regulator 11 of the load current, to the source and substrate of the n-channel after-load transistor 9 and to the power input of the capacitive current generator 12, the first input of which is connected to the second output of the crystal oscillator 6,

The power input of the capacitive current generator 12 is connected to the first plates of both switched capacitors 19 and 20. The second input of the capacitive current generator 12 is connected to the gates of the second and third switching transistors 18 and 21, and the combined substrate and source of the third and fourth switching transistors 21 and 22 are connected to each other with a friend and connected to the second generator output 1 2 capacitive current.

The stabilizer works as follows.

The connection to the stabilizer of the primary power source E causes a single (negative) voltage drop, which through the discharged capacitor 47 (see Fig. 4) is fed to the inputs R of the zeroing trigger 30, 31-45, 46 and to the input S the trigger 49. At the second output of the frequency divider 7 (see Fig. 1), the zero voltage level of the common bus 1 formed by the inverter on the transistor 50 and the resistor 51 appears. The transistor 9 is unlocked and the voltage is set on its drain E. Conditions arose for an accelerated and reliable start of generator 6. A generator 6 start field. Voltage pulses are received at the input of the frequency divider 7. However, the triggers 30, 31-45.46 remain blocked until the voltage at their inputs R exceeds in absolute value the zero threshold of these triggers. After the capacitor 47 is charged through the resistor 48 to the zeroing threshold of the flip-flops, the blocking of the TTT of the flip-flops is removed and the counting of pulses from the first output of the quartz oscillator 6 begins. The zero afterburner signal at the second output of the divider 7 continues until the last trigger 46 hits the trigger pulse at the first output of the frequency divider 7, which controls the stepper motor. After that, the trigger 49 returns to the initial zero state, at the second output of the frequency divider, a single voltage level appears equal to the voltage of the primary power source E |, and on bus 15 a reduced voltage E is established, from which all the triggers of the divider 7 are energized frequencies. Work divides the frequency 7 at a reduced supply voltage E to a value smaller than the sum of two threshold voltages of p and p channel transistors, prevents the occurrence of through-currents in the TT-flip-flops and reduces the power required for reloading these parasitic capacitances triggers.

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Reduced supply voltage; (here and below we are talking about the absolute value of voltages) of a quartz oscillator 6, which is in a stationary oscillation mode, up to a magnitude less than the sum of the threshold voltages of the p- and n-channel transistors eliminates the through-current of the MOSF inverter and reduces the level of energy losses due to overcharging and input and output capacities of the generator. A decrease in the supply voltage or frequency divider 7 eliminates through currents at the moment of switching to the MOS valves and reduces the recharge current and capacitances at the nodes of the frequency divider 7. In this case, the current consumed by the divider 7

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 .f,

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where Cj, is the load capacitance given to the input of the divider;} f is the oscillation frequency of the quartz oscillator.

The presence of negative feedback from the first and second outputs of the generator 6 makes it possible to use the interdependence between the amplitude of the voltage on the outputs of the generator 6 and the magnitude of the voltage to be stabilized E. to increase the system stability.

As parametric voltage stabilizing elements in a MOS clock, input circuits of multi-channel transistors 3 and 13 are used, which are interconnected by a resistor 5.

The level of voltage to be stabilized on bus 15 is determined by the dependence

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Ei U, p + U, -I, -Rj-I-RjH2). (ABOUT

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where and ugi are the threshold voltages of the p- and p-channel transistors 3 and 13; Ig is the capacitor current generator current 12; I - total current consumption

in the bus 15;

 - the influence factor of the substrate of the transistor 13.

In the stationary mode of operation, the MOS clock, when the voltage on the bus 15 is close to the stabilization level E,

Transistors 3 and 13 operate in the region of weak inversion of conductivity of the channel part of the semiconductor surface. In this case, the semiconductor surface potential is within one or two Fermi potentials, and the drain current of these transistors is of the order of 10 nA. This circumstance allows using the input circuits of transistors 3 and 13 as threshold voltage sensors.

Transistor 3 is turned on in the diode mode, the drain current of this transistor is entirely determined by the current of the capacitor current generator 12. The dimensions of the channel of transistor 3 are chosen so that when the current of the generator of 12 capacitive currents varies from 0 to 20 nA, the gate voltage of transistor 3 changes slightly and lies near the threshold voltage of the p-channel transistor. In this case, the transistor 3 operates in a flat area, and its drain current does not depend on the voltage across its drain. The channel size of transistor 4 should be chosen the same as that of transistor 3. In this case, the modes of operation of these transistors will be the same, as their input circuits are connected in parallel. Thus, regardless of the different voltages on the drains of transistors 3 and 4, the drain currents of these transistors are the same. The output circuits of transistors 4 and 13 are connected in series, therefore, in stationary mode of operation, the drain currents of these transistors are the same and equal to the current of the capacitor current generator 12. The channel dimensions of the transistor 13 are chosen according to the same criteria as transistor 3, therefore the input circuit of transistor 13 can also act as a threshold voltage sensor, but already an n-channel transistor.

The current If of the capacitor current generator 12 creates a voltage drop ij on the resistor 5. Ry, which reduces the voltage stabilization on bus 15,

The voltage E is also determined by the current I of the load, which is a crystal oscillator 6 and a frequency divider 7. The voltage drop IR, shifts the substrate of the n-channel transistor 13 in the positive region relative to the source and thereby reduces the threshold

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the voltage of the n-channel transistor 13, at {I, R, 17, where is the influence factor of the substrate. As the current I increases, the voltage Ej decreases, which should cause a slowdown in the load current I. Thus, the resistor R, 4 stabilizes the load current I of the bus 15. In addition to the functions of forming the reference voltage and stabilizing the load current I on the bus 15, transistor 13 performs still function of an active element of the amplifier. The function of the load current generator in this amplifier is performed by transistor 4. The transistor 13 and 4 amplifier is non-inverting, since the active transistor 13 is controlled by a voltage source at the second output of the capacitive current generator 12. The output voltage of the amplifier is applied to the gate of the transistor 11, which controls the load current of the bus 15, the voltage can vary from O to E. The resistance of the resistor 10 must be chosen such that the condition E - E IR, g (1+ g) OPS at any threshold voltages of transistors 3 and 13.

In this case, the transistor 11 can always be locked by the voltage across the drain of the transistor 13, and therefore, the restriction on the use of the K MOS clock circuit at low threshold voltages of the transistors is removed.

In the afterburner mode, the chain from the transistor 11 and the resistor 10 is sequential, shorted by the output circuit of the open transistor 9. In the stationary mode of operation of the device, the transistor 9 is locked with a voltage E at its gate.

45 The main function of generator 12 in current capacity is to form a current (., Which is a function of the parameter of a crystal oscillator 6, which characterizes the stability margin

gQ oscillations in the stationary mode, and the stability margin function of the frequency divider 7. The effective unlocking voltage of the n-channel

gg transistor and, „,. The term “effec- tive unlocking voltage” is understood here as the difference between the double amplitude of oscillations: and the threshold voltage of the n-channel transistor. The charge and discharge of capacitors 19 and 20 are relative to the level E, therefore this level is taken as the zero point of reference for the voltages in the generator 12 of capacitive current. In this case, it can be said that the capacitor 20 in the first cycle is charged through the output circuit of the open transistor 18 to the difference of the voltages

and

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- and. „and

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where and, is the double voltage amplitude at the first output of the quartz oscillator 6, and in the second cycle it is discharged to zero through the output circuit of the transistor 22.

In the second cycle of operation of the capacitor current generator 12, the capacitor 19 is already charged through the output circuit of the open transistor 17 to the voltage difference U - Vgn U, cp, where U, and 2 is the maximum voltage at the second output of the crystal oscillator 6. The capacitor 19 is discharged to zero in the first cycle through the output circuit of the open transistor 21. The capacitor 16 smoothes the inrush current at the output of the generator 12 with a current capacity.

Thus, the average value of the current generated by the generator 12 of the capacitive current is determined by the expression

1c (C, o-e, + C ,,. Ee).

where C, o and the capacity of the respective capacitors, capacitor current generator 12.

The impurities (1) and (2) imply that the resistor Ry, together with the capacitor current generator 12, stabilizes the effective unlocking voltages at the outputs of the quartz oscillator 6, for example, as the effective unlocking voltages at the outputs of the capacitive current generator 12 voltage E on bus 15 is reduced, which should lead to a decrease in the effective unlocking voltage

SRI.

The steepness of the inverting amplifier of the quartz oscillator 6 (see Fig. 3) is chosen such that, for all external destabilizing factors, the supply voltage at which the oscillations of the oscillator 6 fails to be less than the voltage E on the supply bus 15. Generator 6 operation

in the field of supply voltages smaller than the sum of the two threshold voltages of raster-channel transistors, eliminates the possibility of the appearance of through currents in the transistors 23 and 24 of the inverter and minimizes the voltage drops across which the input 27 and output 28 capacitors of the generator are recharged 6. All this leads to a decrease in the energy consumed by the circuit from the power source.

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Claims (2)

1. Voltage regulator power supply clock integrated circuit containing a negative and common bus primary power source, reference p-channel transistor, reference p-channel transistor, crystal, stabilized power bus, frequency divider, output bus and transistor-load current regulator , the common bus of the primary power source is connected to the source and the substrate of the reference p-channel transistor and the common power inputs. a quartz oscillator and a frequency divider whose input is connected to the first output of a quartz oscillator connected by its power output with a stabilized power bus, and the output bus connected to the first output of a frequency divider whose primary power input is connected to the negative primary power bus and the substrate of the transistor-regulator the load current connected by its gate to the drain and the drain to the source of the reference n-channel transistor of the load current controller, characterized in that, in order to reduce the cost power supply, a load p-channel transistor, a capacitor current generator, a n-channel afterburner transistor, and three resistors are introduced into it, the negative bus of the primary power supply connected through the second resistor to the source of the load current transistor, an afterburner channel transistor and with the power input of the capacitive current generator, the first input of which is connected to the second output of the crystal oscillator, the stabilized power bus is connected to the input of the stabilized power supply frequency solver. the second output of which is connected to the gate of the n-channel afterburner transistor, the drain of which is connected to the source of the reference n-channel transistor connected by its drain to the drain of the load n-channel transistor whose substrate and source are connected to the common bus of the primary power source, and the first quartz output the generator is connected to the second input of the capacitor current generator, the first output of which is connected to the gate of the load p-channel transistor, the gate of the reference p-channel and through the first resistor to the drain a p-channel transistor and to the gate of the reference p-channel transistor connected with its source to the second output of a capacitive current generator and through a third resistor with its substrate and with a stabilized power bus. 2. The stabilizer according to claim 1, about tl and - due to the fact that the capacitive current generator contains a smoothing and two switched capacitors and four switching transistors, the power supply of a capacitive current generator connected to the first plates of both switched capacitors and a smoothing capacitor connected by a second plate to the first output of a capacitive current generator and to the drains of the first and second switching transistors, the combined substrates and the source of each of which are connected to drains, respectively, of the third and fourth switching transistors and with the second plates, respectively, of the first and second switched capacitors, the first input of the capacitive current generator is connected to the gates of the first and fourth switching transistors, the second input of the capacitor current generator is connected to the gates of the second and third switching transistors, and the combined substrate and the source of the third and fourth quadrature switching transistors connected to each other and connected to the second output of the capacitive current generator. FI.2 gjus.4