SU1341694A1 - Device for protecting against voltage step-down - Google Patents

Abstract

The invention relates to electrical engineering. The purpose of the invention is to expand the functionality of the device. The goal is achieved by decreasing the voltage of the monitored source by the pulse from the OR element bis of the output of the element OR 7 does not transfer the D-flip-flop 8 to the zero state. At its output will remain a logical unit. At the same time, the logical unit at the output of the logic element AND 10 is the alarm signal, which causes the binary counter 9 and the output D-flip-flop to be reset to zero. Using the invention allows controlling and automatically controlling the switching of the supply voltage of the branched consumers. 2 Il. 1 SL OE 4: 05 SB

Description

The invention relates to protection and automation devices. And it can be used to control and automatically control the switching of the supply voltage of the responsible consumers when they are powered from two common-mode AC sources - the main and the backup.

The aim of the invention is to expand the functionality of the device, increase its speed and reliability,

Fig, 1 shows a functional diagram of the device; Fig. 2 is a time chart of the operation of the device for the case of monitoring a three-phase power source.

The device (FIG. 1) contains input nodes, the number of which is equal to the number of phases of the monitored power source, the input node contains a two-half-period rectifier 1, threshold devices 2 and 3, and two single-oscillators 4 and 5, to the input of the full-wave you 1, the phase voltage of the monitored source is applied, and its output is connected to the inputs of two threshold blocks 2 and 3, the outputs of the thresholds of the blocks 2 of each node are connected to the first logic element OR 6 through the one-oscillator 4, and the other output blocks 3 rators 5 are connected to the input The second of the logical element OR 7, the output of the logical element OR 7 is connected to the R-inlet of the first Gere 8, and the output of the OR 6 is connected to the S-input of the D-flip-flop 8, to the input of the binary counter 9 and to the input of And 10, the forward output of the D-flip-flop 8 is connected to the second input of the 10 And logical gate, and the output of the 10-gates of the logic element is connected to the twist-in input of the binary counter 9 and the R-input of the second D-flip-flop 11 "The output of the binary counter 9 is connected with a counting input of the D-flip-flop 11, and direct and inverse the outputs of D-flip-flop 11 are the outputs of the device that control the switching-on of the main and backup power sources, respectively. In binary counter 9, an output K is used at which the output signal appears when a binary counter 9 arrives at the counting input of a binary counter where n is the phase control phase

 Primer 5,

blown power source, t, e, K 2 "; K - binary counter output 9,. ,

The voltage of the monitored source should not exceed the allowable voltage level at the inputs of the elements from which the specific performance of the device is assumed. Therefore, if necessary, the controlled voltage should be reduced by using, for example, a transformer or voltage divider,

The device operates as follows.

The voltage of each phase of the monitored power source is fed to the input of the corresponding full-wave rectifier, from the output of which the rectified voltage is fed to the inputs of two threshold devices 2 and 3, the threshold devices 2 operate each time the half-wave voltage reaches a certain set value U In this case, the outputs of the one-shot 4 connected to these threshold devices generate pulses of duration

t

 .... T „4 p m

where T is peri At ditch 5,

one; The number of phases of the monitored power source, am-factor, margin. Threshold devices 3 trigger the time when the half-wave voltage reaches some second specified value Uj9 greater than the first, determined by the given level U, which corresponds to the minimum acceptable level of the controlled voltage. For example, when controlling a single-phase power source (IJ-, and when controlling a three-phase source

When s 5,

de and and

. - IT. And .. sin (-arcs in -),

and, the amplitude of the controlled voltage;

a predetermined level for generating pulses when the thresholds of elements 2 are triggered;

level 5 corresponds to the minimum allowable voltage,

In this case, at the outputs of one-shot znankh with threshold devices 3, pulses of the same duration are formed.

The pulses generated by the single-shotrs 5 when the threshold devices 3 are triggered, through the logic element OR 7, are fed to the dipstick input of the D-flip-flop 8. Each of these pulses sets the D-flip-flop 8 to the zero state, which corresponds to the appearance at the direct output of the D-flip-flop 8 of the low potential level (logical O), the pulses formed by the single-oscillators 4 when the threshold devices 2 are triggered, through the logical element LI 6 are fed to the counting input of the D-flip-flop B D-trig- ger 8 in a single state, which corresponds to the occurrence of direct th output high potential level of D-flip-flop 8 (logic 1),

At the same time, each of these pulses is fed to the counting input of the binary counter 9 and to one input of an AND 10 logic element, to the other input of which a signal is output from the D-flip-flop 8, With stable operation of the monitored power source at the inputs of the AND 10 logic element the appearance of any combination of signals, except for the simultaneous appearance of two logical 1, therefore the output of the logic element I 10. is a logical O, which does not affect the output state of the D flip-flop 11. The binary counter

9 counts the pulses of the same sequence, and after the binary counter 9 2p arrives at the input of its output, a pulse appears,

arriving at the counting input of the D-flip-flop 11, the leading edge of this pulse, the D-flip-flop 11, is set to one state, which determines the switching on of the main and off of the backup power sources. A decrease in the voltage of the monitored power supply at least in one of the phases to a level lower than the permissible level leads to the fact that by the time a pulse appears from one of the inputs of a logical element AND 10 from the output sequence of an OR 6 element, the pulse from the output sequence of an OR 7, arriving at the zero input of the D-trigger 8 as a result of a temporary

ten

th

- - nt in g-)

to

15

20

25

thirty

the shift caused by the decrease in voltage does not yet translate the D-flip-flop 8 to the zero state and on its output connected to the other input of the AND 10 logic element there remains a logical 1. In this case, the output of the AND 10 logic gate is the logical 1 - alarm signal causing nullification of the binary counter 9 and the output D-flip-flop. The zero state of the D-flip-flop determines, for example, connecting the consumer to the backup power source and disconnecting it from the main power source,

Fig. 2 shows that decreasing the amplitude of the half-wave voltage, for example, in phase A by the value of uU, causes a time shift by the value ut of the corresponding pulse from the output of the logical element OR 7,

The use of the invention allows the control and automatic control of the switching of the supply voltage of the responsible consumers when they are powered from both single-phase and multi-phase AC sources. This increases the speed of the device, especially when controlling multiphase power sources. The maximum response time to is always less than the next high-,

where T is the period.

35 faces:

T 2: n

An is the number of phases of the monitored power source. In addition, the device is not sensitive to a decrease in the frequency of the monitored voltage and is not sensitive to an increase in the frequency of less than m times,

Claims (1)

Invention Formula An anti-undervoltage protection device f containing an input node consisting of a two-period rectifier, whose input has terminals for connection to the phase of the monitored voltage, and output to the inputs of the first and second threshold blocks and two single-oscillators of the OR logical element and the switching element with two stable states, characterized in that 4TOj in order to expand the functionality of the device, increase its speed at and nadnosti, a second OR element, an AND element, a binary pulse counter, a D-flip-flop with a counting input and a switching circuit with two stable states, which is made on a D-flip-flop with a counting input, the device is supplied with a number of input nodes equal to the number of monitored voltage phases, the outputs of the first and second threshold blocks are connected respectively to the inputs of the first and second one-voltage circuits, the outputs of which are connected respectively to the first inputs of the first and second element OR, the output of the first element OR is connected to Compiled by V. Balashov. Editor T. Parfenova Tehred L. Serdyukova Order 4441/55 Circulation 617 Subscription VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 6 counting inputs of the binary counter of the first D-flip-flop and with the first input of the AND element, the output BTOpof o of the OR element is connected to the R-input of the first D-flip-flop, whose D- and S-inputs are combined and connected via a resistor to an additional voltage source the output of which is connected to the second input of the element AND the output of the element AND is connected to the zero inputs of the binary counter and the second D-flip-flop, the D- and S-inputs of the second D-flip-flop are connected to each other and are connected via a resistor to an additional voltage source, to the counting input B -trigger A binary pulse output is connected. Proofreader A, Zimokosov