SU1332558A1 - Device for detecting signals with double relative phase-shift keying - Google Patents

Abstract

The invention relates to radio engineering and can be used in the stepwise reception of discrete messages. The purpose of the invention is to improve noise immunity. The device contains a generator 1, phase shifters 2 and 3 at 90 °, phase shifter 4 at 45 °, shapers 5 and 6 pulses, low pass filters 7 and 8, delay lines 9 and 10, adders 11, 12 and 13, integrators 14 and 15 and multipliers 16-25. The goal is achieved by the introduction of phase shifters 3 and 4, filters 7 and 8, adder 13 and multipliers 22-25, which are used for phase detection of inter-orthogonal components of the delayed and non-delayed radio signals, resulting in the formation of sign output scrolls proportional to the cosine and sine phase difference of the received signal. 1 il. i (L with co 1chE SP el 00

Description

The invention relates to radio engineering and can be used in the stepwise reception of discrete messages.

The purpose of the invention is to improve the noise immunity,

The drawing shows a structural electrical circuit of the proposed device.

A device for detecting signals with double relative phase shift keying includes generator 1, first 2 and second 3 phasers by 90 °, phase shifter 4 by 45, first 5 and second 6 pulse shapers, first 7 and second 8 low-pass filters, first 9 and second 10 delay lines, the first 11, the second 12 and the third 13 adders, the first 14 and the second 15 integrators, the first - the tenth multipliers 16-2

The device works as follows.

The received radio signal arriving at the device input is converted by multipliers 16 and 17 with mutually orthogonal reference oscillations of the same frequency, taken from generator 1 and split by 90 ° using a phase shifter 2 by 90 °.

As a result of the correlation transformation of the received radio signal, for which the quasi-harmonicity condition is satisfied (the carrier frequency is many times greater than the frequency band occupied by the manipulated radio signal), with reference oscillations whose frequency is close to the carrier, at the output of the integrators 14 and

15 receive two quadrature projections XI., 1 Y., In the form of low-frequency convolutions (results) at a near-zero intermediate (differential) frequency, since high-frequency conversion products formed at the output of multipliers

16 and 17 of the sum frequency are attenuated by integrators 14 and 15 as low-pass filters. These integrators 14 and 15 have a forced discharge reset to the zero state by briefly shorting the capacitor plates and at the moments of the boundaries of the parcels.

Further by these low-frequency results X,

and y, d realized

There are balanced modulation of the main axis-orthogonal reference oscillations (multipliers 24 and 25). Each of the multipliers 24 and 25 at its output forms two sidebands (upper and lower relative to the frequency of the reference oscillation). Due to the combination of two input quadrature low-frequency signal convolutions and two mutually orthogonal reference oscillations and replacing the addition in adder 12 with subtraction, it is possible to obtain a sine or cosine component of one of the two sidebands of an unused radio signal S,

(t) so

as a composition

The other side bands are mutually compensated.

In addition, the low frequency convolution signals X., and Y., the received radio signal, and the interorthogonal reference oscillations are stored for the duration of the sprinkling with delay lines 9 and 10.

According to the detained results X,

form similarly to restoration of an unused radio signal S, (t)

components

mutually orthogonal, (t)

S (t) and S (t) delayed radio

The same sideband (quadrature radio signal S (t) differs from Sp (t;) by a constant phase turn of 90 °). For additional phase rotation of the delayed radio signals, the reference oscillation, taken from the common generator, is additionally phased at an angle of 45 ° with four gradations of the phase of the received radio signal with phase shifts Oj 90 180 and 270 ° or angle O with eight gradations of phase 45 manipulation; 135; 225 and 315 ° with a phase shifter 4 into 45, after which the reference oscillation is split into inter-orthogonal oscillations by means of a phase shifter 3 into 90 °.

Additional inter-orthogonal reference oscillations are modulated

corresponding low frequency convolution signals in multipliers 18-21. From the outputs of adders 11 and 12, the mutually orthogonal components S (t) and S (t) of the delayed radio signal are sent to the second inputs of the multipliers 22 and 23, which, in combination with the filters 7 and B, form channel phase detectors. The first inputs of the transceiver 22 and 23 (of these phase detectors) receive an unimproved radio signal of the same frequency as the delayed one. Due to the possibility of phasing the quadrature components of the delayed radio signal relative to the delayed one, it becomes possible to demodulate the same DFM radio signal path with various modifications of the manipulation code. Phase detection of quasi-harmonic radio signals with indispensable frequency selection in the video signal band using low-pass filters 7 and 8 allows for better quality detection compared to signal detection at the near-zero intermediate frequency of a known device when attenuation of unnecessary multiplication products becomes impossible.

As a result of phase detection (a combination of multipliers 22 and 23), the mutually orthogonal components of the delayed and non-delayed radio signals form sign output voltages proportional to the cosine and sine of the phase difference of the received signal.

Claims (1)

Invention Formula The DD1I device for detecting signals with double relative phase shift keying contains a generator whose output is connected to the first input of the first multiplier and to the input of the first phase shifter through 90 °, the output of which is connected to the first input of the second multiplier, the second input of which is connected to the second input of the first multiplier, the output of which is connected to the first input of the first integrator, the output of which is connected to the input of the first delay line, the output of which is connected to the first input of the third multiplier and to the first in the fourth multiplier, the output of which is connected to the first input of the first adder, the second input of which is connected to the output of the fifth multiplier, the first input of which is connected to the output multiplier Order 3850/56 the house of the second delay line the input of the sixth multiplier of which is connected to the first 1 of the second adder, the second of which is connected to the output of the multiplier, the output of the second multiplier is connected to the second integrator, 10 is connected to the input of the second holder, and two formers, wherein the second input of the multiplier is to the input of the device, the clock 15 of which the second inputs of the first and second repeaters are, the outputs of the device with the outputs of the first and second () n, exc. 20 This is due to the fact that, from noise immunity, four multipliers, two low frequencies, the second phase by 90, the phase shifter on C adder, the output of which is with the first inputs of the eighth of the eighth multipliers, the inputs of which are connected respectively to the first and 30 adders, the output is generated with the first input of the nine multipliers and with the input of the phase of 45, the output of which with the second input of the fifth trans -jTj with the second input of a generous body and with the input of the second fl of 90, the output of which is the second input of the third ne and with the second input the quarter 40 multiplier, the output of the first tel by 90 is connected to the fifth class, and the multiplier is connected to the first third adder, the second 45 is connected to the output d of the multiplier, the second input is connected to the output of the second torus, the output of the first is integrated with the second input dec 50 multipliers, the outputs of the seventh multipliers by the connections of the first low-pass filters, respectively, are connected to the inputs from cs but the first and second pulse forms. Circulation 638 Subscription Random polygons pr-tie, Uzhgorod, st. Project, 4 the house of the second delay line and the first input of the sixth multiplier, the output of which is connected to the first input The second adder, the second input of which is connected to the output of the third multiplier, the output of the second multiplier is connected to the first input of the second integrator, the output of which connected to the input of the second delay line, and two pulse drivers, while the second input of the peruguos multiplier is the signal input of the device, clock input which is the second combined inputs of the first and second integrators, the outputs of the device are the outputs of the first and second drivers () n, which is different from the fact that, in order to improve noise immunity, the introduction of four multipliers, two low-pass filters, the second phase shifter at 90, the phase shifter at 45 ° and the third adder, the output of which is connected to the first inputs of the seventh and eighth multipliers, the second inputs of which are connected to the outputs of the first and second, respectively adders, the generator output is connected to the first input of the ninth multiplier and to the input of the phase shifter at 45, the output of which is connected to the second input of the fifth multiplier, with the second input of the multiplier and with the input of the second phase shifter 90, the output of which is connected to the second input of the third multiplier and the second input of the fourth multiplier, the output of the first phase shifter 90 is connected to the first input of the tenth multiplier, the output of which is connected to the first input of the third adder, The second input of which is connected to the output of the ninth multiplier, the second input of which is connected to the output of the second integrator, the output of the first integrator is connected to the second input of the tenth multiplier, the outputs of the The eighth and eighth multipliers are connected to the inputs of the first and second low-pass filters, respectively, the outputs of which are connected to the inputs of the first and second pulse shapers, respectively.