SU1332522A2 - Adaptive delta movdulator - Google Patents

Abstract

The invention relates to automation and communication technology. The use of the invention in various data transmission systems makes it possible to increase the accuracy of the delta modulator operation by reducing distortion overload. The adaptive delta modulator contains a comparator 1, a D-flip-flop 2, a half-adder 3, a delay counter 4, a reversible counter 6, controllable keys 7, a resistive matrix 8, and an integrator 9. The introduction of a controllable frequency divider 5 ensures that the large slope of the increments will remain large signal level 1 il. i

Description

The image relates to automation and communication technology, can be used in various data transmission systems and is an improvement of the invention in accordance with the authors. St. No. 1246379.

The purpose of the invention is to increase the accuracy of the device by reducing distortion overload.

The drawing shows a functional diagram of an adaptive delta modulator.

The adaptive delta-modulator contains a comparator I, D-flip-flop 2, half-adder 3, delay counter 4, control frequency divider 5, reversible counter 6, control keys 7, resistive matrix 8 and integrator 9. The drawing denotes the information and clock inputs 10 and 11 and exit 12.

Adaptive Delta-modulator works as follows.

The first input of the comparator 1 from input 10 receives an input analog signal, and simultaneously to the second input to which the integrator 9 is connected, an approximating voltage arrives, which is determined by which of the keys 7 commute the outputs of the resistive matrix 8. The error signal arising when comparing the input analog signal and approximating voltage, it is quantized by the level of the comparator 1 and is fed to the first input of the half adder 3 and to the information input of the O-flip-flop 2. From the output of the D-flip-flop 2, the information goes to the common resist point The output matrix 8 is used to control the polarity of the increments and to the second input of the half adder 3, where the parity of the information formed at the output of the comparator 1 occurs with the information delayed by the O-flip-flop 2.

In the case of the same value of the information signals F, the increase or diminution of the input analog signal of the semi-adder 3 enters the counting enable signal into counter 4 delays. The delay time counting time of the delay counter 4 is preset depending on the intended purpose of the delta modulator. When the counter reaches 4 delays of the set value, it is blocked by the prohibitory input and

from its output, a signal is issued to enable the counting to the control input of the reversible counter 6. The same signal sets the division factor equal to one on the controlled frequency divider 5. Thus, the pulses arriving at the counting input of the divider 5 from the clock input 11.

are transmitted to the counting input of the reversible counter 6, which is allowed to score in the key. A change in the number in the reversible counter 6 leads to a change in the position of the keys 7 and,

therefore, the change in the total resistance value of the resistive matrix 8, i.e. to a change in the integrator time constant 9. As a result, an approximating voltage is incremented with a corresponding amplitude and polarity.

In the case of a sequence of information signals of different values (no change in the input analog signal), a logical unit signal is generated at the output of the juusmatmator 3, which resets the delay counter 4. At the same time in the management of

In the splitter 5, the division factor is changed by the specified set number (n), and in the reverse counter 6 a subtractive counting position is set, which reduces the recorded numeric code with a frequency that is n times less than the clock frequency. Thus, the decrease in the value of the numeric code in the reverse counter 5 occurs

the selected number of times is slower, which allows one to maintain a large slope of increments at high signal levels.

Thus, overload distortion is reduced with abrupt changes in the input signal, which leads to greater accuracy in the operation of the adaptive delta modulator.

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F o rm ula invention

The adaptive delta modulator, according to aut. No. 1246379, differs by the fact that, in order to increase the device operation accuracy by reducing distortion overload, a controllable frequency divider, counting and control inputs are introduced

31332522

which are connected, respectively, of the molded frequency divider is connected to

to the clock input of the device and to the computational input of the reversible counter-, the delay counter, the output of the controller.

Claims (1)

Claim Adaptive delta modulator, according to autosw.No 1246379, characterized in that, in order to increase the accuracy of the device by reducing distortion overload, a controlled frequency divider is introduced, the counting and control inputs of which are connected respectively to the frequency divider connected to the clock input devices and to the calculating input of the reversible counter of the delay counter, the output of the manager. Editor N. Lazarenko Compiled by O. Revinsky Tehred L. Serdyukova Proofreader E. Roshko Order 3848/55 Circulation 901 Subscription VNIIIPI of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4