SU1332311A1 - Device for classifying the picture elements - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to reduce equipment. The device contains sorting units 1-6, delay units 7-9. The effectiveness of the proposed device is to reduce the cost of the equipment, namely, to exclude the comparison element from the device. 1 hp f-ly, 4 ill.

Description

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The invention relates to computing.

The purpose of the invention is to reduce equipment.

Figure 1 shows the layout of the device; figure 2 - diagram of the delay element; on fig.Z - the first scheme of the sorting block; figure 4 is a second diagram of the sorting unit.

The device contains sorting blocks 1-6, blocks 7-9 delay, information inputs 10-14, outputs 15 and 16, inputs 17 and 18 synchronization, registers 19 and 20, input 21 and output 22 of the delay element, registers 23-28 circuit 29 comparisons, element 30, inputs 3.1, 32 and outputs 33, 34 of the sorting unit, registers 35-46, comparison circuit 47, element 48, inputs 49- .52 and outputs 53-56 of the sorting unit.

A device for sorting image elements works as follows.

The unit arranges the image elements arriving at the inputs 10 and 11 of the device. At the outputs of block 1, the elements of the image are contained, nor A1 and A2, respectively, where A1, A2. Block 2. Ordering reads the image elements arriving at the inputs 12 and 13 of the device. At the outputs of block 2, they contain: mc picture elements A3, A4, respectively, where AZ / A4. In block 6, A1 and A3 are compared and the maximum number is placed on the first output of block 6, and the minimum of A1 and A3 is placed on the second output of block 6. To keep the order of A2 and A4 relative to A1 and A3, A2 is placed on the third output of block 6 A4 is placed on the fourth output of block 6, if, in the case of AKAZ, A4 is placed on the third code of block 6. and on the fourth output of block 6 is placed A2. Thus, the first output of block 6 contains the maximum element A1, at its output - elec

A3, for which the condition is fulfilled. Element A4 is located at the fourth output of block 6, and element A2 is at its third output, for which condition A25A1 is fulfilled. Consequently, the input of block 4 receives the maximum element A (the fourth in ascending order) of the elements arriving at the inputs of the device 10–13.

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By sorting A2 and A3 in block 3, the third in ascending element of the four compared elements arriving at the inputs of the device 10-13 is determined. It is implied that the first ascending element is the minimum element of the compared elements. As the number increases, the element size increases. Thus, at the first output of block 6 and the first output of block 3, two of the largest elements of the four are compared. The blocks 4 and 5 are used to insert the fifth element coming at the device input 14 into the sequence of the two largest elements ( of the four compared), ordered among themselves. Thus, at the output of block 9, i.e. output 15 contains the maximum element of the five compared (fifth element ascending), and the first output of block 5 contains the fourth ascending element of the five compared. Delay units 7-9 are designed to store pixels in those comparison cycles in which they do not participate in comparison operations. The comparison kp includes the passage of sync signals through the clock inputs 17 and 18 of the device. The sync signals at input 18 of the device are phase shifted relative to the sync signals at input 17. On the positive edge of the sync signal at input 7, the registers 19 of delay blocks 7–9 as well as the registers 23, 24, and 35–38 are written to registers 19. On the positive edge of the sync signal at input 18, information is recorded in registers 20, 25-28 and 39-46. The separation in time of recording data (pixels) into delay blocks and sorting blocks and changes in the information on their outputs will eliminate the phenomenon of races in the process of receiving and transmitting data. In scheme 29, an operation is performed to subtract from the contents of register 25 the contents of register 26. If the contents of register 25 are greater than the contents of register 26, then the output of circuit 29 is zero, so that information from the outputs of registers 25 and 26 is allowed. from the compared pixel (from the register 25), If the output of the circuit 29 is one

is equal, then the contents of register 26 are greater than the contents of register 25, and similarly the contents of register 28 are greater than the contents of register 27, The single value of the output of circuit 29 to the zero signal, inverted by element 30, allows information from the outputs of registers 27 and 28. Thus, output 33 a larger image element from register 28 enters, and output 34 is a smaller element from register 27. In circuit 47 (FIG. 4), the operation of subtracting register 40 from the contents of register 40 is performed. If the contents of register 39 are larger than -register 40, then the output of circuit 47 is zero, while the output of information from the outputs of registers 39, 40, 43 and 44 is allowed. At output 53, a larger element A1 is received from register 39, at output 54, element A3 is received from register 40, and output

55 enters the element from the register 43, on the output 56 comes from the

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gistra 49 element. If the output of circuit 47 is single, then the contents of register 40 are greater than the contents of register 39, and similarly the contents of register 42 "are greater than the contents of register 41. The unit-inverted output of NE 48 does not allow the output of information from the outputs of registers 41, 42 45 and 46. Thus, at the output 53, the maximum A1 element from the register 42 arrives. At the output 54, the element A3 arrives from the register 41 At the output 55, the A2 element comes from the register 46, where. To the exit

564 element A4 is received from register 45, where A4 is AZ.

Claims (2)

1. A device for classifying image elements, containing; its six sorters, their blocks and three delay units, the first and second information inputs of the first sorti er block are respectively the first and second information inputs of the device, the first and second information inputs of the second the sorting block are the third and fourth information inputs of the device, respectively; the fifth information input of the device is connected to the information input of the first block in 5 0 five oh oh five " with supports, in order to reduce the equipment, in it the outputs of a larger number of the third and fourth sorting blocks are connected respectively to the first information input of the fifth sorting block and to the information input of the second delay block, the output of a smaller number of the fourth sorting block is connected to the second the information input of the fifth sorting unit, the output of a larger number of which and the output of the second delay unit are outputs of the device, the outputs of a larger number of the first and second block sorting in connected respectively to the first and second information inputs of the sixth sorting unit, the third and fourth informational inputs of which are connected respectively to the outputs of a smaller number of the first and second sorting blocks, the first output of the sixth sorting block is connected to the first information input of the fourth sorting block, the second and third outputs are connected respectively with the first and second information inputs of the third sorting unit, the output of the first delay unit is connected to the information input t The second delay block, the output of which is connected to the second information input of the fourth sorting block, the first and second synchronization inputs from the first to the sixth sorting blocks and the first to third delay blocks are connected respectively to the first and second synchronization inputs of the device. 2. The device according to claim 1, characterized in that the sixth rotating unit contains twelve registers, the comparison circuit and the element NOT, and the information inputs of the registers one through four are respectively the first, second, third and fourth information inputs of the block, the synchronization inputs the first, second, third and fourth registers are connected to the first synchronization input of the block, the information outputs of the fifth and sixth registers are connected respectively to the first and second inputs of the comparison circuit. The code of the first register connected to the informational inputs of the fifth and seventh registers, the output of the second register is connected to the information inputs of the sixth and eighth registers, the output outputs of the fifth and eighth registers are connected to the first output of the block, the outputs of the sixth and seventh registers are connected to the second output of the block, the synchronization inputs From the 1st to the 12th is connected to the second synchronization input of the block, the third register output is connected, to the information inputs of the ninth and eleventh registers, the fourth register output a union of ten data inputs Z1 / 3 additions of the ninth and twelfth registers are connected to the third output of the block, outputs of the tenth and eleventh registers are connected to the fourth output of the block, the output of the comparison circuit is connected to the input of the element NOT and to the permission inputs of the fifth, sixth, nine In addition to this and the tenth of the registers, the output of the element is NOT connected to the inputs of the resolution of the seventh, eighth, eleventh and twelfth registers. W 22 17 eight 2 W 35 J5 35  fM  h four / 4-2 5J L  f 3 H J 77 /I Editor E. Papp Compiled by A. Zherenov Tehred I.Popovich Order 3833/44 Circulation 672 Subscription VNR1IPY USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 C 53 five 5s 5U - Figm Corrector V. But ha