SU1330738A1 - Pulse shaper - Google Patents

Abstract

The invention can be used in digital automation devices and computing equipment for generating pulses of stable duration. The pulse shaper contains RS-flip-flop 1, comparator 3, timing circuit 4 on resistor 9 and capacitor 10, diode 11, bus 7 and 8, resistors 2, 6 and 12. The stability of the duration of the generated pulses is ensured by the fact that The ratio between the voltage to which the capacitor 10 tends to charge and the threshold voltage, resulting in the charging time of the capacitor 10 until the trigger 1 returns to its initial state, is almost independent of the voltage of the source n tani. In this case, the duration of the generated pulses is determined only by the parameters of the time of the driving circuit. 2 Il. with (L with with with About vl with 00

Description

The invention relates to a pulse technique and can be used in digital automation devices and computer technology to form impulses of stable duration.

The purpose of the invention is to expand the range and increase the stability of the duration of forming 1 1 impulse.

FIG. 1 is an electrical circuit diagram of the device; in fig. 2 - timing charts of its elements.

The pulse shaper contains the RS-flip-flop 1, the first resistor 2, the comparator 3 and the time of the driving circuit 4, per Bbiii the input of which is connected to the first output of the pepper resistor 2, and the trigger code is connected to the inverting comparator 3 whose output is connected to the R-input of the RS-flip-flop 1, the S-input is SOEDIN G with the INPUT lUUIioi l S formatir pulses; the second resistor 6, the inverse input F S-ipnrrepa 1 is connected to the first output voltage 7 of the pulse shaper and through the second resistor 6 it is connected to the comparator's inverting input and the second output of the first resistor K1, pr / -: 1 the 1st output of the RS flip-flop is connected to the first input is the time of the master circuit, the second input of which is connected to the common voltage of the pulse former, the second output bus 8 is connected to the code of the comparator 3, lying 1 can be done on the integrating circuit of the series-connected resistor 9 and the capacitor 10 resistor 9 a follower is shunted; about the combined diodes 11 and the fourth resis-1-orom 12.

Form1 puller operates as follows).

In the initial state on the entry spike 5 is high level 1 (Fig. 2a, spacing,). At the same time, the direct output of the RS flip-flop O (FIG. 2b), 1 — on the output bus 7 ((1; ig. 2c); the inverting input of the comparator 3 maintains the level O {fig.2g, interval tj, -t , dashed line L1ii1), and non-inverting - positive voltage level (Fig. 2c, interval, solid line), determined by a resistive divider formed by resistors 11 2 and 6, as a result of which the output of the comparator 3 is supported by level 1 (Fig, 2d , interval to-t,).

When a pulse O is applied to the input bus 5 (Fig. 2a, time t), trigger 1 is switched to one state, at which level 1 is set at its direct output, and level O is set at output bus 7 (Fig. 26c. Moment t,). Trigger trigger

1 is hopping, as the voltage at the output of the comparator 3 in

this moment is kept high due to the fact that the voltage at its non-inverting input exceeds the voltage at the inverting input. At the moment when the flip-flop 1 trips, the voltage difference at the inputs of the comparator 3 increases, since from the direct output of flip-flop 1 through a resistor

2, the non-inverting input of the comparator 3 receives a positive voltage level, through the resistor 6 of the inverse Biiixo, aa - zero level, and the resistance value of resistor 2 is selected less than the resistance value of resistor 6.

From this moment on, the charge of the capacitor 10 starts charging circuit 4 through a resistor 9, and the capacitor 0 tends to charge to level 1

(Fig. 2d, spacing, dashed

LITP).

At the moment of time when the voltage level at the inverting input of the comparator 3 begins to exceed the level of the voltage w at its non-inverting input, the output of the comparator 3 is set to O (fig.2g, d, time t). If the duration of the input pulse is less than the duration

the generated pulse, trigger 1 jumps to a position in which the direct output of trigger 1 is stopped: the level O is applied, and you - X.- The front bus 7 is level 1 (Fig. 2b,

at, moment 2

 the end of the output pulse, a recovery process occurs in which the capacitor 10 is discharged. P 1cr d. Occurs on the circuit: resistor

9, the low output impedance of the flip-flop of the trigger 1. Since the voltage across the direct output of the trigger 1 through the resistor 9 is transmitted fia non-inverting input

comparator 3 (fig. 2d, solid line, time tj), the output of comparator 3 maintains the level O (fig.2d, interval) until the voltage at the inverting input becomes lower than the voltage level at the non-inverting input (fig. 2c, moment tj). This moment ends the formation of a pulse at the output of the comparator 3, i.e. additional pulse on the output bus of the pulse shaper.

In those cases when a second pulse of relatively long duration is not required, to reduce the recovery time in parallel with resistor 9, a diode 11 is connected by an anode by time to a driving capacitor 10.

To adjust the duration of the pulse formed on the output bus, resistor 12 is connected in series with diode 11.

Claims (1)

Formula The pulse shaper containing RS-trigger, the first resistor, the company t, tj figure 1 Editor M. Dylyn Compiled by, Chizhikov Tehred M. Hodach h Corrector A. Tsk Order 3592/56 Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113033, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 307384 RATOR and time is the driver circuit, the first input of which is connected to the first output of the first resistor, and the output is connected to the inverting input of the comparator, the output of which is connected to the R-input of the RS flip-flop, the S input of which is connected to the input bus of the pulse former, which differs 10 so that, in order to expand the range and increase the stability of the duration of the generated pulses, a second resistor is inserted into it, the inverse output of the trigger is connected to the output bus of the pulse former, and through the second resistor is connected to a noninverting input house comparator and a second terminal of the first resistor, a direct output RSi-flop is connected to By the first input, the time of the master circuit, the second input of which is connected to the common bus, the second output bus is connected to the output of the comparator.