SU1327185A1 - Memory location - Google Patents

Abstract

The invention relates to computing and can be used in storage devices. The aim of the invention is to increase speed. The goal is achieved by inserting a shunt element and a key transistor into the memory cell, the collector of which is connected to the p-base of the thyristor, and the base and emitter are connected to the write bus and to the p-base of the thyristor, respectively. 5 il.

Description

11327185

The invention relates to computing and can be used in storage devices.

The aim of the invention is to increase speed.

Figure 1 shows the principle

g

behind

cell diagram in FIG. 2 shows the construction of cell regions in FIG. 3 — the equivalent cell diagram in FIG. 4 is the diagrams of control and feeding impulses; FIG. 3 shows the dependence of the switching voltage of the cell (on the anode) on the amplitude of the power pulse supplied to the additional p-region.

Memory cell contains p-region

1p-pp-structure (anode), p-base

2p-pp-structures, 3p-pp-structures, p-emitter 4 (cathode) pp-p-structures, base 5 key. transistor j key transistor emitter 6, Schottky barrier diode 7, shunt element 8, read and write buses 9 and 10, information

and a total of 11 and 12, hide the p-layer 13, p-p-p-ip-p-p-transistors 14 and 15, capacitance 16 and 17 (C1 and C2), capacitance 18. (СЗ) pnpn structures, shunt 19 (14-19 elements of the equivalent pnp structures), nnpn transistor 20, diode 21 with Schottky barrier.

In Fig. 4, the following symbols are accepted: 22 — first power pulse, 23 — second power pulse, 24, 25 — power pulses passing to bus 12 (in the state of cell 1), 26 and 27 — read pulses, 28 - a write pulse of state O, 29 — coordinate coordinate pulse of write 1 (on a horizontal bus), 30 — coordinate write pulse 1 (on a vertical bus), 31-33 — interference pulses arising on bus 12 when writing or reading O, 34 — read pulse 1 on bus 12.

Pnpn Structures with two thin bases have the dependence of the switching on voltage on the amplitude of the pulse charging the barrier capacitances of the structure. This dependency is for the structure shown in FIGS. 1 and 2

, can be expressed by the formula and (2 § i) + E (1+

and

imp. bkl

C2

C2

),(one)

where and is the threshold voltage otpi 2

pn-junction wounds (, 5B);

C1, C2 - barrier capacitances of pnpn structures; . Е is the amplitude of the charge pulse.

The dependence (1) at C1 "C2 is shown in figure 5 ,,

Pulsed power of the storage cell is carried out periodically

the next with a frequency of about 10 - 10 Hz pulses of positive polarity (22,23) with a duration of about 10 -10 s, and the pulse 22 is fed to the bus 9 (anode pnpn-structure), and the pulse 23, the next, directly behind the pulse 22, is fed to the bus 10. The load resistance must be included in the bus 12 circuit. The memory cell may be in state 1 (low turn-on threshold voltage) and in state O (large turn-on threshold voltage).

In state 1, impulse 22 includes a pnpn structure (1–4), and impulse 23 extracts the charge of minority carriers arising in its bases through the np transition (2.3) and partially through n- p-transition (1,2). The reverse resorption current should be limited by the load resistance in the bus 10 circuit.

The charge extracted by pulse 23 is limited so that by the end of the pulse the containers 16, 17 (01.02) are not charged yet. Such a limitation can be achieved as a limitation of the current of the inverse spread 35 40 45

gg

55

and the limitation of the pulse duration 23. Since after the termination, the action of the pulse 23 of the tank 16, 17 is not charged, the next pulse 22 in accordance with formula (1) includes. The pnpn structure 1-4 and state 1 is maintained,

In state O, pulse 22 does not include a pnpn structure because the amplitude of the switching voltage is greater than the amplitude of pulse 22. For example, if the amplitude of pulse 22 is 2B and the amplitude of pulse 23 is 3V, then According to (1), neglecting some of the bits 16, 17 due to leaks (see Fig. 5), the switching voltage of the switch-on voltage is close to the PS and the pulse 22 does not include the pnpn structure. The impulse 23, immediately following the impulse 22, resumes the charge of the capacitances 16, 17 (C1, C2), h313

The one that was lost during the time between the queues by the pairs of supply pulses 22, 23. This pulse provides a given level of noise immunity of the memory cell in the state O.

O is recorded between the power pulses (see Fig. 4). To do this, a positive potential is maintained on bus 11 by locking the pn junction 5-6, and bus 10 is supplied with a pulse 28 of positive polarity, the amplitude of which is E. The coincidence of the positive voltage on bus 11 and the impulse voltage on pn 10 cause charge barriers 16, 17, corresponding to a higher threshold turn-on voltage of the p-ti-pn structure (O state). When using a Schottky barrier diode (21 or 7) in the charge circuit, the duration of the write pulse O is practically limited only by the RC time constant. When using the bus 10 connection only to the p-region 5, the speed is somewhat reduced due to the recovery time of the transition 5-2.

Recording 1 is performed by applying a pulse 29 to the bus 10 and removing the blocking voltage on the bus 11 (pulse 30). At the same time, the capacitance 17 of the collector pn-junction (C2) is discharged through the transistor, formed by layers 2,5,6 (Fig. 1), shunt 8 (see Fig. 3 — transistor 20, shunt 19). The discharge of capacitance C2 (C2 C1) is equivalent to writing t

About 5 0 5

0

five

0

854

In order to construct a memory matrix, it is sometimes necessary to prohibit writing to certain cells of a word, for example, writing 1 for the first bit, without changing the contents of the record in the adjacent bits. A recording can be disabled by applying a positive polarity pulse to bus 12. In this case, applying a pulse to bus 10 does not result in O recording, because the potentials on buses 10 and 12 are not applied. Pulse supply to bus 12 does not cause a change in the records in cells with C1; C2.

The memory cell can be used to construct various systems of storage microminiature matrix devices with low power consumption. For the manufacture of memory cells, a technological circuit with dielectric isolation, isolation of pn-junction using a hidden layer can be used.

Invention The memory cell contains a thyristor, the anode and cathode of which are connected respectively to the readout bus and the common bus, characterized in that, in order to increase the speed of the memory cell, a key transistor and a shunt element are inserted into it, and the transistor is connected to the p-base of the thyristor, the base and the emitter are connected respectively to the recording bus and the cell information bus, and the first and second terminals of the shunt element are connected respectively to the cathode and the p-base of the thyristor.

. 2

T T T PR T

T

T,

2Q

21

011

120

fi9.3

Fiyo. four

itmp

ten

YU

Editor I.Rybchenko

Compiled by L. Amuseva

Tehred L. Oliynyk Proofreader L. Pilipenko

Order 3404/49 Circulation 589 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

Claims (1)

Formulas of the invention Memory cell _; containing a thyristor, the anode and cathode of which are connected respectively to the read bus and the common bus, characterized in that, in order to increase the speed of the memory cell, a key transistor and a shunt element are introduced into it, the key transistor collector connected to the thyristor p-base, the base and the emitter is connected respectively to the write bus and the information bus of the cell, and the first and second terminals of the shunt element are connected respectively to the cathode; and the η-base of the thyristor. tPiJ8. t of FIG. 3 1327181 22 26 27 22 U ______ □ ____ D ___ □ _ 24 π I 24 nA ⁵ ky D n .................... nff FIG. 5