SU1319270A1 - Electronic switch - Google Patents

Abstract

The invention relates to a pulse technique and can be used in switching devices. The purpose of the invention is to increase reliability and speed. The device contains two series-connected transistors 1 and 2, the control unit 3. In the device entered two elements And 4 and 5, two elements 6 and 7 of the delay. The drawing also shows the device output 8, the power supply strips 9 and 10, the start input 11 and the reset input 12 of the control unit 3. The introduction of new elements and interconnections eliminates the simultaneous presence of both transistors in the open state, i.e., the flow of through currents is prevented when control pulses enter the input, and the switching time is determined only by the on and off times of the two transistors. 2 Il. Yu cl oo with to

Description

The invention relates to a pulse technique and can be used in switching devices.

The purpose of the invention is to increase reliability and speed.

FIG. 1 shows the flowchart of the electronic key; in fig. 2 - time diagrams of voltages.

The electronic key contains the first 2 and second 2 transistors of the same conductivity type, control unit 3, the first 4 and second 5 elements And, the first 6 and second 7 delay elements. The first and second outputs of the control unit are connected respectively to the inputs of the first and second delay elements and the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the outputs of the first and second delay elements, the outputs of the first and second elements AND are connected respectively to the base. the first and second transistors, while the collector of the first transistor is connected to the emitter of the second transistor and to the output 8 of the electronic key, the emitter - to the negative pole 9 of the first power source Ui, the collector of the second transistor is connected to the positive pole 10 of the second power source Ua, the control signals are fed to the start input 1 and the reset input 12 of the control unit. The delay elements 6 and 7 — typical elements, for example, LC or RC-type, provide an input signal delay by time ts equal to the blocking time of transistor 1 or 2. Control unit 3 is used to convert the input pulse signals into paraphase potential signals. An R-S trigger can be used as a control unit.

The electronic key works as follows.

In the initial state, in the absence of a control signal at the start input of the control unit, the first transistor is closed (Fig. 2i), the second transistor is open {Fig. 2k). The closed state of the first transistor is provided by the presence of the signal "O on its base (Fig. 2g), which comes from the output of the first And 4 element, which has on its inputs signals" O, coming directly from the first output of the control unit 3 (Fig. 2c) and through the first element 6 of the delay (Fig. Zd). The saturation mode of the open second transistor 2 is provided by the presence of the signal "1 (Fig. 2h) at its base, which comes from the output of the second element And 5, which has at its inputs the signals" 1, coming directly from the second output of the control unit (Fig. 2d) and through the second delay element 7 (Fig. 2c). As a result, a positive voltage level U2 is formed at the output of the electronic key (Fig. 2n).

When a pulse arrives at the start input (Fig. 2a), the signal "1 (Fig. 2c) appears at the first output of control unit 3, which is fed to the first input of the first

element 4 and the input of the first delay element 6, from which the signal "1 (Fig. 2e) arrives with a delay of time ts 1 off to the second input of the first element 4, after which the signal" 1 "is formed at its output (fig. 2g ) and for time

1 on; ta opens the first transistor 1 (Fig. 2i). Simultaneously with the formation of the signal "1, at the first output of the control unit 3, at its second output, a signal" O (Fig. 2d) is formed, which strikes the input of the second delay element and the first input of the second element 5, resulting in no delay regarding the arrival of the signal triggering the output element And the signal is formed "O (Fig. 2h), which is supplied to the base of the second transistor 2 and

0 closes it during 1v off 1z (Fig. 2k), as a result switching of transistors occurs and at the output of the electronic key a negative voltage level Ui is formed (Fig. 2n), which is different

f is from the negative voltage level Ui by the voltage value on the internal resistance in the saturation mode of the first transistor 1.

The arrival of a pulse at the reset input (Fig. 26) leads to the return of the electronic key to its initial state. At the same time, the first transistor 1 without delay relative to the time of arrival of the reset pulse begins to close (Fig. 2i), since at its base the signal "O (Fig. 2g) appears, and the second transistor 2 through

5 time per tBK time. opens (Fig. 2k) with the signal "1, arriving at its base (Fig. 2h). At the output of the electronic key, a positive voltage level LJ2 is formed (Fig. 2L).

Thus, the cumulative positive effect — an increase in reliability and speed — is achieved by eliminating the simultaneous presence of both transistors in an open state, i.e., the flow

5 through-currents as the control pulses enter the input, and the switching time is determined only by the on and off times of the two series-connected transistors of the electronic key.

50

Claims (1)

Invention Formula An electronic switch containing two series-connected transistors, the common connection point of which is connected to the output of the switch, and a control unit, characterized in that, in order to increase reliability and speed, transistors of the same type of conductivity are used in it and the first and second elements And the first and second delay elements are introduced, the first and second outputs of the control unit are connected respectively to the inputs of the first and second delay elements and to the first inputs of the first and second elements And, the second inputs of which are connected to the outputs the delay elements, and the outputs of the And elements, respectively, with the bases of the first and second transistors, the emitter of the first transistor is connected to the negative pole of the first power source, the collector of the second one is connected to the positive pole of the second power source. 2