SU1319047A1 - Analog multiplying device - Google Patents

Description

one

The invention relates to electrical computing devices and can be used in analog computers.

The aim of the invention is to improve the accuracy of work.

Figure 1 is given a functional diagram of an analog duplicating device; 2 is a simplified diagram of the device.

The device contains the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh scale resistors 1-11, respectively, the first 12 and second 13 bias resistors, a balancing potentiometer 14 the first 15, the second 16 and the third 17 operational amplifiers, the first 18 and second 19 field-effect transistors, the zero potential bus 20, the inputs of the first 21 and second 22 signal-soms of the scissors, the input 23 of the bias voltage setting, the output 24.

The device works as follows.

The voltage of the second signal multiplier from the input 22 is supplied to the scale unit formed by the third operational amplifier 17, the first 18 and the second 19 field-effect transistors. The gain factor of the scale unit at the inverting input is equal to the ratio of the conductivity of the second field-effect transistor 19 to the conductivity of the first field-effect transistor 18.

The voltage of the first signal multiplier from input 2 through the second one amplifier 6 is fed to the gate of the second field-effect transistor 19 and changes proportionally to its conductivity, i.e. the gain of the scale block varies in proportion to the voltage of the source of the first signal factor. As a result, the output voltage of the scale unit, equal to the product of its gain and the voltage of the source of the second signal factor, is proportional to the product of the voltages of the first and second factor signals.

To compensate for the nonlinearity of the characteristics of the first 18 and second 19 field-effect transistors, the voltage of the first signal multiplier from the input

190472

21 is supplied via the second 16 and first 15 operational amplifiers to the gates of the second 19 and first 18 field-effect transistors, and the output voltage from the third operational amplifier 17 is supplied via the first operational amplifier 15 to the gate of the first field-effect transistor 18. In addition, the voltage of the second signal 0 multiplier from input 22 enters

through a voltage divider formed by the eighth 8th and ninth 9th scale resistors to the non-inverting input of the third operating amplitude of 5 liters to ensure that the voltage at output 24 is equal to zero when the source voltage of the first signal-multiplier from input 21 is equal to input 23

 sets the operation mode of the first 18 and second 19 field-effect transistors in the middle of the linear sections of their control characteristics.

The balancing potentiometer 14 provides the ability to eliminate the imbalance of the device due to the non-identity of the first 18 and second 19 field-effect transistors.

 The proposed multiplier device provides for compensation for the dependence of the transfer coefficient on temperature. For analysis, consider the simplified functional diagram 35 of the analog duplicating device in FIG.

The transfer ratio is described by the expression

40

45

V - l. f & (14

  r p and) {, q (jg + b, GIB

where Gg, the conductivity of the eighth

8 and nine that 9 scale. resistors; G, g, G |,) - conductivity of the first

18 and second 19 field effect transistors.

From the expression (D) it follows that, depending on the conduction temperature 50 of the first 18 and second 19 field-effect transistors, are included in the expression as a ratio. Consequently, when their parameters vary with temperature, the ratio should be almost constant, especially when the field-effect transistors are identical.

Therefore, the proposed analogue multiplying device is characterized by a higher accuracy of operation due to the provision of the effect of thermal coercion of the parameters of field-effect transistors.

Claims (1)

Formula i and t An analog multiplying device containing the first, second and third operational amplifiers, the first and second elements with controlled resistance, made respectively on the first and second field effect transistors, the first large-scale resistor, the first output of which is connected to the non-inverting input of the first operational amplifier and the first pin of the scale resistor, the second pin of which is connected to the drain of the first field-effect transistor, the first pin of the third large-scale resistor is connected to the inverting input of the first The first amplifier is connected to the output of the first operational amplifier and to the gate of the first field-effect transistor. The second switch of the first offset resistor is connected to the first terminal of the balancing potentiometer, the second switch is connected to the first. The input of the second bias resistor, the average output of the balancing potentiometer, is the input to set the bias voltage of the device to a non-inverting In the course of the second operational amplifier, the first terminals of the fifth and sixth scale resistors are connected, the first terminal of the seventh scale resistor is connected to the inverting input of the second operational amplifier, the output of which is connected to the gate of the second field-effect transistor; with the first outputs of the eighth and ninth large-scale resistors, the second output of the eighth large-scale resistor is connected to the second drain the second transistor of the first, third, and sixth scale resistors are connected to the zero potential bus; the tenth and eleventh scale resistors, characterized in that, in order to improve operation accuracy, the source of the first field-effect transistor is connected the output of which is the output of the device and connected to the drain of the first field-effect transistor, the second output of the seventh scale resistor is connected to the output of the second operational amplifier, to the inverter The second input of the second bias resistor and the first one of the ten scale resistor, the second one of which is the input of the first multiplier signal, the non-inverting input of the first operational amplifier, is connected to the first input of the second output elec- the scaling resistor with the drain of the second field-effect transistor and is the input of the second signal multiplier, the second output of the ninth scaling resistor. connected to a zero potential bus. 22 2