SU1319022A1 - Calculating device - Google Patents

Abstract

The invention relates to computing, and can be used in floating point processors that contain a hardware multiplication unit. The aim of the invention is to enhance the functionality by performing multiplication. This goal is achieved by the fact that the device containing 2-4 comparison circuits with zero, AND 5-8 elements, blocks 9-12 of units, contains switch 1 and multiplication unit 13 with appropriate connections. 1 ill., 1 tab.

Description

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The invention relates to computing and can be used in floating point processors that contain a hardware multiplication unit.

The aim of the invention is to enhance the functionality of the device by performing multiplication.

The drawing shows a diagram of the computing device.

The device contains a switch 1, comparison circuits 2-4 with zero, AND elements 5-8, memory blocks 9-12, multiplication unit 13, device shift direction input 14, device output 15, first and second information outputs 16 and 17 of the device and input 18 task-device mode.

Multiplication unit 13 is matrix. Blocks 9-12 of memory are implemented on permanent storage devices (ROM). The numbers above the harnesses in the drawing indicate the communication width.

The device works as follows.

The number to be normalized, from input 16, is fed to the inputs of circuits 2-4 comparing with zero. Beginning with the higher bits, groups of bits of the original number are analyzed. The size of the group is determined by the address width of the selected permanent storage devices. In this case, when the ROM address is equal to eight and the original number is thirty two, the number of ROM is four.

Each group of eight bits, except the last one, is fed to circuits 2-4 comparing with zero and blocks 9-11. The last group comes only at block 12. Comparison schemes with zero in combination with the elements 5.7 and. 8 is used to select the desired memory block. It happens as follows. Each group of eight bits enters its comparison circuit with zero. If all the bits in the group are equal to zero, then at the output of the comparison circuit with zero a logical one is formed and zero is formed otherwise. Suppose the highest group is not zero, i.e. one or several bits are equal to one, then a logical zero is formed at the output of circuit 2 comparing with zero. This zero input to the inputs of the elements And 5 and 6, prohibits the passage of signal190222

fishing through the elements And 5.7 and B, i.e. Prohibits the reading of information from blocks 10-12. At the same time, at the inverse output of circuit 2 of comparison with 5 zero, a logical unit is formed that allows reading information from block 9, where the value of the shift parameter is stored. The shift parameter is determined by the number of zeros to

fO the first significant unit in the block 9 address (see table).

At the output of each memory block, eight bits are formed, containing 5 either zero or one in only one bit. The correspondence between the shift parameter and the bit number in which the unit stands is shown above. Multiply the received operand

20 by the original number in block 13 multiplication, we obtain the product of the original number by the power of two, which corresponds to the shift. However, in this way, you can only move to the right;

25 to organize the left.shift, read the result not from the older part but from the younger part. Then, making, for example, a shift of 25 bits to the right and reading the information, starting with

30 32 bits for 63, we get the original number shifted by 7 bits to the left. This operation is performed by switch 1 at the signal from input 14. If the first eight bits are equal

35 to zero, then a logical unit is formed at the forward output of the comparison circuit 2, and a logical zero is formed at the inverse. Scheme 3 compares the next group of eight.

40 bits If it is not null, then a logical zero is generated at the output of the comparison circuit with zero. As a result, signals are formed that prohibit reading from blocks 11 and

45 12, and on the element 5, a signal is generated that permits reading from block 10. The shift parameter is formed in the same way as described, except that the fact of zero equal eight preceding eight bits is taken into account. This count is made by adding to the number of shifts in this group the number eight. Then a shift is formed according to the described algorithm.

55 In the same way, the definition of the shift parameter and the shift itself for the following groups of bits are made. The only exception is the value of the number that needs to be added.

Each group increases it by eight, i.e. in the first +0 in the second +8, in the third + 1b, in the fourth +24.

The shift to the right is performed similarly, for this purpose, a number containing only one unit in any category is inputted to input 17. All blocks of memory are disconnected by a signal from input 18, when the selector 1 selects the most significant bits of the product. To multiply to input 17, a factor is fed (the second operand), switch 1 selects a number in two cycles: in the first cycle the upper part, in the second, the lower part of the product.

Claims (1)

Invention Formula A computing device containing three comparison circuits with zero, four AND elements and four memory blocks, the inputs of the address bits of the first, second, third and fourth memory blocks are connected, respectively. with the bit inputs, in addition to the senior, first information input of the device, the bit inputs of the first, second and third comparison circuit with zero are connected respectively to the bits of the bits, besides the senior and seven junior, first information input of the device, the inequality output of the first equation circuit zero is connected to the readout input of the first memory block, the equality output of the first comparison circuit with zero is connected to the first inputs of the first and second I elements, and output 00111 00110 00110 00101 five 5 o five The inequalities and equalities of the second comparison circuit with zero are connected respectively to the second inputs of the first and second elements And, the output of the second element And connects to the first inputs of the third and fourth elements And, the second inputs of which are connected respectively to the outputs of inequality and equality of the third comparison circuit with zero, the outputs of the first, third and fourth elements And. are connected respectively to the read enable inputs of the second, third and fourth memory blocks, the read inhibit inputs of which are connected to the input setting the device mode and with the input of the prohibition of reading the first memory block, which is in order to expand the functionality by performing multiplication, it contains a switch and a multiplication unit, the first information input of the device connected to the input of the first multiplier the multiplication unit, the outputs of the higher and lower parts, whose products are connected respectively to the first and second information inputs of the switch, the output of which is the output of the device, the second information input and input The shift directions of which are connected respectively to the input of the second multiplier of the multiplication unit and to the control input of the switch, the outputs of the bits of the memory blocks from the first to the fourth are connected respectively to the inputs of the bits of the second multiplier of the multiplication unit. 24 25 25 26 00001000 00100 00010000 00011 00100000 00010 01000000 00001 10,000,000 00000 11111111 00000 Or A.Vorovich 2513/43 Compiled by A. Klyuev Tehred M. Khodanych Co Po Circulation 672 VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 27 28 29 thirty 31 31 Proofreader I.Musk Subscription