SU1317364A1 - Device for digital measuring of acceleration - Google Patents

Abstract

The invention relates to computing and can be used in high-precision systems for automatic control of the speed or position of actuators with elastic kinematic coupling and phase position sensors. The purpose of the invention is to increase the reliability of the device by simplifying its circuit. At the end of each period of operation, frequency divider 2 into two pulse shaper 3 outputs two consecutive pulses, by which the number accumulated in counter 7 is written to register 10 and counter 7 is reset to prepare it for the next clock cycle. A negative number is represented in the counter 7 by a reverse code and an EXCLUSIVE OR 11 scheme converts it into a forward code. The transformation is controlled by the sign bit i CO with co 05 4 fict

Description

113

The invention relates to computing technology and can be used in high-precision systems for automatically controlling the speed or position of executive mechanisms with elastic kinematic coupling and phase position sensors.

The purpose of the invention is to increase the reliability of the device by simplifying its circuit.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 voltage slots at the outputs of the circuit blocks, explaining the operation of the device

The device consists of a zero-speed frequency sensor 1, a divider 2 frequencies into two, a B-trigger} driver of 3 pulses, a generator k of stable frequency pulses, keys 5 and 6, a reversible counter 7 consisting of the trigger 8 of the lower bit and the block 9. including all other bits of the register register 10, the decoder 11, which is a block of circuits of the two-code OR 12 circuit of the two-code OR of the counter. The input 14 of the zero-body 1 receives the voltage from the output of the phase or pulse-type sensor (not shown) of the frequency. the output 15 of the zero-body 1, which is the output of the sensor, is connected to the input of the splitter 2 frequencies into two, the direct code 16 of which is connected to the input of the driver 3 of the pulses and the first input of the key 5, and the inverse output, 17 is connected to the first input of the key 6, The first bit 18 of the imaging unit 3 pulses is connected to the register write resolution 10 input, and the second output 19 is connected to the zeroing input of the high-level bits of the counter and to the first input of the OR circuit 12. The output 20 of the generator 4 is connected to the second inputs of the keys}, outputs 21 and "22 which are connected respectively to the inputs of the summation and subtracting the trigger 8 low-order counter Counter My output 23 low-order bit 8 is connected to the zero input of the low zero section of the counter, with the second discharge input of the counter included in block 9, the first input of the register 10, inverse Output 24 - from the subtraction input of the counter bits. Output 25, the loan counter 7 is connected to the input

42

block 13, and the counting outputs 26 are connected; Units with inputs of register 10, outputs 27 and 28 of which are connected to the inputs of the EXCLUSIVE OR or sign

device output. The output 29 of the ORDERING OR circuit is the output of the device, the output 30 of the unit 13 is connected to the second input of the OR circuit 12, the output 31 of which is connected to

input zero reset trigger 8 low bit counter 7.

The device works as follows.

When going through zero for example

five

0

five

ki u.j, sensor output winding

the zero-body 1 forms rectangular pulses that are fed to the input of the divider 2 by two. Direct 16 and inverse 17 outputs of divider 2 Hai two control the first 5 and second 6 keys, passing pulses of the high-frequency generator 4 to the summing and subtracting inputs of the reversing counter 7, at the end of each period of operation of the divider 2 into two pulse generator 3 pulses consecutive pulses 18 and 19, by which the number accumulated in

 counter 7, into register 10, and resetting the counter to prepare it for the next clock cycle. Negative Number Represented in the counter as a reverse code, therefore, an EXCLUSIVE OR scheme has been introduced that converts it into forward code 29. The conversion is controlled by the significant bit 28 of register 10.

 О Thus, during the first period, the voltage U (Tdp,) in the reversible counter is summed up by the pulses of the generator, and during the second () is subtracted. While rotating

45 objects with speed q; the frequency of the output signal of the position sensor varies according to the law

f

AP

 f 21e

(one)

where fjj is the frequency of the sensor supply.

Consequentially} if the object is stationary or rotates with a constant speed, then T, P1 Td "1 and by the end of the second period Ng 0. When the object rotates with acceleration T d" t to the moment of reading, the code in the counter is greater or less than zero depending on the

313

directions of rotation, therefore, a value of Ng different from zero is obtained:

NC (Tdsch Tdp1

) f, (-l -, - l-) f.

- ff

 dpg

Uji

2TG

Ji l--) 2tr

) (fc) L 1 L1 ± 1A11

r

(f + 4i -) (f + -1.) 0 - 2 P ° 2

Lui

w

T.e; the output code of the device is proportional to the acceleration t of the object. Here U), and to, are the average values of the velocity of the object over a period, and Td, respectively. Values (f | 5 ± o) and

Wi

(fg i o-) cause non-linearity

the meter, however, with real values of f (2.5-10) kHz and (a) / 2 "-)" d 20-60 Hz, the latter can be neglected and the characteristic should be considered linear:

N

S.L11

H

(3)

in the proposed scheme, when the counter code 7 goes over, in the zero-subtraction mode (from 000. .00 to 1.11 .. 11), there is a loss of information corresponding to one pulse, since both numbers in the forward and reverse codes, respectively, are zero, To avoid this and thereby increase the accuracy of measurement, it is necessary to translate the counter code when subtracting from 000 ... 00 to 111 ... 10. To do this, the device additionally introduces the OR 12 circuit and the low-zero circuit 13 of the counter 7. Its output 30 is set to 1 when the counter code 7 is zeroed by the signal from the counter 25 output and acts through the OR circuit 12 on the R input of the trigger minor bit counter. Installing the latter in O locks the resetting circuit.

This bit is 13 by the signal from output 23, and further subtraction occurs, starting with code 1111 .., 10.

Claims (1)

J. Claim Formula A digital acceleration measurement device containing a frequency speed sensor, two keys, a reversing 10 pulse counter, a generator, a decoder, the output of the speed sensor connected to the first inputs of the keys, the second inputs of which are connected to the generator outputs, and the outputs of the first J5 and second keys are connected to the inputs summing and subtracting respectively a reversible counter connected by its outputs to the inputs of the decoder, characterized in that 0, in order to improve the reliability of the device, two D-triggers, two The tail OR circuit, the memory register and the pulse shaper with two outputs, the rear 5 front of the pulse from the first output coincide with the leading edge of the pulse from the second output, while the sensor output is connected to the input of the first D-flip-flop, - 0 is not directly connected to the pulse driver input and the first input of the first key, and its inverse output is connected to the first BbtM input of the second key, the first output of the pulse driver is connected to the memory register write enable input, and the second output is connected to zeroing inputs MSB counter and to the first input circuit I-Uffl, a second input connected to 0. the output of the second B-trigger connected by the input to the counter credit output, the output of the OR circuit is connected to the low-zero input of the counter connected by the direct output to the second-bit input of the second discharge of the second D-trigger and the first register input , and the inverse output — with the subtraction input of the higher bits 0 of the counter, the outputs of the higher bits — of the counter are connected to the inputs of the higher bits of the register, the outputs of which are connected to the inputs of the decoder and the sign output of the device. % fig Compiled by V.Pimerov Editor A.Revin Tehred M.Hodanich Proofreader G. Reshetnik. Order 2417/40 Circulation 776 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4