SU1316006A1 - Analog-digital adder - Google Patents

Abstract

The invention relates to hybrid computing and can be used in the construction of specialized computing devices aimed at solving systems of algebraic differential and difference equations. The aim of the invention is to improve the accuracy and resolution of the adder. The analog-digital adder contains a digital p-bit combinational adder 1, analog inverter 3, first comparator 4, RS-trigger 5, second comparator 6, first 7, second 8 and third 9 keys, first, second, and third buses of reference voltages 10, 11 and 12, inputs 13 and outputs 14. Achieving the goal is achieved by introducing into the digital combinational adder an additional analog discharge containing an analog adder with four inputs, an analog inverter, a comparison circuit RS trigger, two comparators, first, second and third to Yuchi and m new bonds between these elements. 1 il. (Oh (ln: o 05 o o 05

Description

113

The invention relates to computing, in particular to hybrid computing, and can be used to build specialized computing devices for solving algebraic and differential equations and many other applications.

The aim of the invention is to improve the accuracy and resolution of the adder.

The drawing is a diagram of (n + 1) —discharge analog-digital adder.

The adder contains a digital-p-rand DNY combinational adder 1, analog adder 2, analog adder 2, analog inverter 3, first comparator 4, RS flip-flop 5, second comparator 6, first key 7, second key 8, third key 9 , the first bus 10 of the reference voltage corresponding to the digital unit, the second bus 11 of the reference voltage corresponding to the analog transfer unit, the third bus 12 of the reference voltage corresponding to the inverted digital unit, inputs 13 and outputs 1Д.

The higher-order transfer output of the digital p-bit combinational adder 1 is connected to the control input of the first key 7, the output of which is connected to the first input of the analog adder 2 with four inputs. The output of the analog adder 2 through an analog inverter 3 is connected to the first input of the comparator 4, the second input of which is connected to the bus 10 of the reference voltage of the digital unit. The output of the comparator 4 is connected to the S setup input of the trigger 5, the output of which is connected to the control input of the second key 8 and to the control input of the third key 9. The input of the third key 9 is connected to the bus 12 of the reference inverted digital unit voltage, and the output with the second input of the analog adder 2. The output of the second key 8 is connected to the low-voltage bus of the digital n-bit combinational adder I. The output of the analog adder 2 is connected to the first input of the comparator 6, the second input of which is connected to the bus zero potential, and the output - with the R input of the RS-trigger 5. The information input of the first key 7 is connected to the bus 11 eta62

analog voltage of the unit of analog transfer, and the information input of the second key 8 with the bus 10 of the reference voltage corresponding to

digital unit. The third and fourth inputs 13 of the analog adder 2, together with the ne 5th and second inputs of the 13 n bits of the digital n-bit combiner adder 1, are

two (n + 1) -digit inputs 13 of the device, and the output 14 of the analog inverter 3, together with the outputs 14p of the digital n-bit combiner combiner 1, is the output of the (n + 1) -th digit of the adder. Consider the operation of the adder with examples of summation of numbers for, i.e. when the device contains three digital one-digit adders

for summing whole parts and one analog bit for summing fractional parts of numbers.

In the binary number system any number can be represented

binary digit sequence

., ... v:, oto, ui,, (1)

where is OL; either O or 1, and the comma separates the integer part from the fractional part.

This record corresponds to the sum of the powers of 2 taken with the coefficients specified in it

p m - about

0.2-s „., 2 + ... + ,, 2 ci, 2

+ o6., 2 + ...

For we have, 2

(2)

, 2 + oi, 2 + ot, 2 2. (3)

In this expression, the three most significant digits of the number are given to specify its integer part and the lower order to specify its fractional part. As can be seen from (3), in the fractional part of the number, only zero can be given

unit with a weight of 0.5.

In the proposed adder, the least significant bit is analog, the principle of which is based on the summation of currents. Information at its entrances

can be set to any voltage level from zero to one volt.

Expression (3) for a given totalizer can be represented as

, 2 × 2%. /, (4)

where g is the base of the number system (not necessarily binary);

3

, oh, PI - chnse.h g-th system

numeration (for takes any value from a number of characters 0,1,2 ,, .., 9). Thus, if the unit levels in the digital adder 1 are set by the voltage 1 V, then in the analogue discharge, for example, with (in decimal number system) the input information (the fractional part of the numbers can be set with any voltage level from permitted levels: 0.0 V, 0.1 V, ... 0.9 V.

We consider the operation of the proposed adder under the assumption that its analog low-order bit works with a decimal number system.

Example 1. Let it be necessary to find the sum Y of the numbers x, 1.6 and x, 8 i.e.,

 , 6 + 1,, 4.

(five)

The operation of the adder starts from the moment when the reference voltage corresponding to the digital unit is applied to the bus 10, - B (with the binary number system in the digital adder 1); on the bus 12 of the reference voltage corresponding to the inverted digital unit - L 1 V; on the bus 11 of the reference voltage corresponding to the unit of analogue transfer and 0.1 V (i.e., the analogue discharge is fractional in the decimal number system, the transfer to this bit has the weight of the least significant unit of the same bit and is set to 0 1) I

The binary codes of the integer parts of the X, and x components (0.01 and 001, respectively) are summed in a three-bit digital adder 1, and the fractional parts of the x, and x components are specified on the third and fourth inputs 13 of the analog adder 2 as voltages, respectively equal to +0.6 V and +0.8 V and summed up in analogue bit.

The output voltage of the analog adder 2 L „„ should vary from

2 EXIT

the zero level to the level - (0.6 + 0.8) -1.4 V, and the voltage at the output of the inverter 3 and, -, respectively, from well 5 рЫ I

of the left level to the level of +1.4 V. However, when the voltage U, g reaches the level of 1 V, the comparator 4 is triggered and sets the RS flip-flop 5 to one state on the S input. A single signal from the output of the RS-flip-flop 5 open64

the second key 8 is injected, and the Tpt-xpas-digital digital adder 1 is transferred from the bus 10 of the reference voltage corresponding to the digital unit to the unit of the reference voltage corresponding to the digital unit, a unit level is applied. A single signal from the output of the RS-flip-flop 5 simultaneously opens the third key 9, and to the second input of the analog adder 2 from the bus

12 of the reference voltage corresponding to the inverted digital unit, a voltage equal to -1 V is applied. Consequently, the voltage U, is set at the output of the analog adder 2. - (0.6 + 0.8 Vr (W

-1.0), 4 V, and the output of the analog inverter 3 is the voltage U

 WY1 (

+0.4 V.

At the outputs of 14 three-digit digital

level adder 1 is set

including transfer from analog bit code

001 - the whole part of the 1st number, 001 - the whole part of the 2nd number, 5 001 - transfer from the lower order

011 - part of the amount is intact.

Thus, the part of the resulting sum of the numbers x, and x, j is equal to (011) 2

Q 3 |, the pp a fractional part of the same numbers, obtained at the output 14 of the analog discharge, is (0.4),. Finally we have the correct result, 6 + 1.8 3.4.

Example 2. Circular (cyclic) transfer adders are used to sum numbers that are specified in forward and inverse codes: the positive numbers correspond to the direct code, the negative ones to the reverse. The most significant bit is significant, and the sign bit O corresponds to a positive number, and I to a negative number.

According to the general rule

5 for finding the inverse code of a negative number, for negative decimal numbers, for example, dp, 6 and, 8, the backward ones are respectively (2,), 3, (h arr

0 where symbol 9 (by analogy with binary symbol 1) in the sign bit indicates that this code is negative.

5 Example. Let it be necessary to obtain the sum Y of numbers x, -1.6 and, 8,, 6-1,, 4. The inverse binary codes of the integer parts of the numbers x and x are, respectively, (110), and

110), j, where the third most significant bit is significant. The inverse decimal codes of the fractional parts of the numbers x and xp are equal to 9.3 and 9.1, respectively, where the second bit is significant. In the considered adder, the sign of the digit is in the higher order of the digital three-digit adder 1. This sign is equally regarded as integer parts, numbers, and to its fractional part. Therefore, the fractional part of the numbers x and x is given as voltages of 0.3 V and 0.1 V, respectively, without a sign bit.

So, when setting the initial information in the digital three-bit adder 1, a single signal appears on the circular (cyclic) transfer line arriving at the control input of the first key 7. The first key 7 opens, and from the reference voltage 11, corresponding to the unit of analog transfer, the first input of analog adder 2 receives the reference voltage of the unit of analog transfer U, equal to and 0.1 V (the younger unit of the fractional part of the decimal number). As a result, the output voltage of the analog adder with four inputs 2 and "becomes equal to

 6bt

 - The output voltage of the analog inverter 3 and, therefore, the voltage on the output bus 14 of the analog discharge becomes equal

and + (0.1 + 0.3 + 0.1) +0.5 V. Zvyh

On the output buses 14 of the digital three-bit adder 1, the codes are set:

110 - the whole part of the 1st number, + 110 - the whole part of the 2nd number,

000 - transfer low-order bits

1100 - part of the amount intact

 - unit circulation

(cyclic) transfer to the low-order bit 50 of the device.

Thus, the whole part of the obtained sum of numbers x and x is (100) 2 -3.0, and the fractional part of these numbers is +0.5. Convert the fractional part

VNIIPI Order 2365/52

Random polygons pr-tie, Uzhgorod, st. Project, 4

5 0 5 About

five

five

0

from the return code to the direct with the sign. The reverse code of the fractional part with a sign is 9.5. From here the direct code is - (9.9-9.5) -0.4.

We finally have the correct result.

, + x,, 6-1 ,,, 4.

Claims (1)

Invention Formula An analog-to-digital adder containing a digital p-bit combinational adder, the two inputs and the output of which are respectively digital information inputs and a digital output of the adder, characterized in that, in order to increase accuracy and resolution, it contains a series-connected analog adder and inverter, RS-trigger, first and second comparators and the first, second and third keys, informational inputs of which are connected to the first, second and third buses of the reference voltages, output The first, second, and third keys are connected respectively to the first input of the analog adder, to the low-order transfer bus of the digital n-bit combinational adder and to the second input of the analog adder, the third and fourth inputs of which are additional analogue information inputs the digital adder, the control input of the first key is connected to the high-order transfer bus of the digital n-bit combinational adder, and the control inputs of the second and third keys are connected to the output of the RS flip-flop, the setup inputs of which are connected to the outputs of the first and second comparators respectively, the inputs of the first comparator are connected respectively to the information input of the first key and to the output of the inverter, and the inputs of the second comparator respectively to the output of the analog adder and the zero potential bus, the output of the inverter is an additional analog output of analog-digital adder. Circulation 672 Subscription