SU1315941A1 - Control device for stepping drive - Google Patents

Abstract

The invention relates to the field of automation and can be used in stepper-drive control systems. The purpose of the invention is to expand the functionality and the region B-J wH% to the Zty power bus. The application of the device for controlling the stepper drive, which is achieved by the introduction of new blocks and functional connections, provides control of the stepper drive with both a number-pulse code and an analog signal. The device contains an amplifier-adder 1, a source of the reference voltage 2, a threshold element 3, elements 4, 5 and 6, elements SH 7, 8 and 9, a pulse generator 10, a 1K flip-flop 11, a frequency divider 12, a delay element 13, inverters 14 and 15, reversible counter 16, digital-to-analog converter-17, decoder 18, key block 19, power amplifier block 20, and stepper drive 21. 1 sludge. o (L I P-, fmnn J (SSh1Pt gJL in Ui rri f9 - € rt about 21 oo SP; about 4;

Description

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The invention relates to automation and can be used in estimates of control with an electric and electro-hydraulic stepper drive, with an analog representation of the control signal.

The purpose of the invention is to expand the functionality and scope of the device for controlling the stepper drive.

On. The drawing shows a functional diagram of the proposed device in the case of analog control of a 4-phase stepper motor.

The device contains an amplifier-sum matrix 1, a source 2 of the reference voltage, the threshold element 3, the first 4, the second 5 and the third 6 elements AND, the first 7, the second 8 and the third 9 elements OR, the generator 10 pulses, 1K-Trig ger 11 , frequency divider 12, delay element 13, inverters 14 and 15, reversible counter 6, digital-to-analog converter 17, decoder 18, key block 19, power amplifier block 20, and stepper drive 21.

The pulses of the generator 10 through the element And 6, the element OR 9 and one of the elements AND 4 or 5 are fed to the counting inputs of the counter 16. The output signals of the latter, corresponding to the younger bits, are sent to the decoder 18, in which they are converted into the corresponding combinations of phase windings stepper motor, the output signals of the decoder 18 are passed through the block 19 keys, block 20 power amplifiers and fed to the stepper drive 21. In the output information of the counter 16 through the converter 17 is fed to the subtracting first input of the amplifier 1 and, on the other inputs of which are supplied to the control and reference signals respectively.

The device works as follows

In the initial state, in the absence of an input signal, the number in the reversible counter of 16 pulses corresponds to half of its full capacity, and the output of the digital-to-analog converter contains a signal equal to the reference voltage at the input of the amplifier-accumulator. The zero state of the least significant bits of the counter-16 corresponds to a certain state of the outputs of the decoder 18, for example & p, respectively 159412

corresponding to the first and second thermal phase phase windings of the stepper drive 21.

When a control signal appears at the input of amplifier-suppressor 1, a difference signal (error) is generated at the output of the latter, which can be either positive polarity or negative polarity. At 0, horn element 3 implements a three-position relay characteristic. At the first output of the threshold element 3, the logical unit is formed in the event that a positive error signal exceeds a predetermined threshold value, and at the second output, if the module transforms the negative error signal of the same threshold value. Thus, depending on the mismatch sign, the counting pulses generated by generator 10 through elements 4 or 5 are passed to the summation or subtraction input, respectively. The resolution of the passage of the counting pulses is formed by the element OR 7 in the presence of at least one logical I at the output of the threshold element 3. At the same time, the first counting pulse, immediately following the appearance of the logical 1 at the output of the element OR 7, passes through the AND 6 element, since 11 - trigger 1 1 for the duration of this pulse saves

35 is the unit state at the inverse output, which ensures the presence of logical 1 and the third input of the element 6.

On the trailing edge of the first counting pulse, the 1K-trigger is set to the zero state by the inverse output, at the third input of the AND 6 element is also logical O. The pulses from the pulse generator 10 through the AND 6 element are prohibited, and the counter 16 receives the pulses from the divider 12 frequencies through the element OR 9 and the elements AND 4 or 5. The division factor of the divider is 12 hours and 50 so that the reversing counter 16 receives pulses with a frequency equal to the operating frequency of the stepper drive.

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Under the action of the pulses arriving at the counter 16, the content of the latter is increased (or decreased) until the corresponding output voltage of the digital-analogue voltage

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(the transformer 17 cannot be compared with the control signal 1M signal at the input of amplifier-resistor 1. Logic O is set up at the outputs of threshold element 3. Logic O is also set at the first input of the element 6, and logical 1 at the input of the zero frequency zeroer, as a result, the formation of counting pulses is stopped.

In the process of recalculation, the minor bits of the counter 16 change their state, which with the help of the decoder 8 is transformed into the appropriate combinations of the included phase windings of the stepper motor. The drawing shows an example of the implementation of a decoder for a 4-phase pair-commuted motor. The switching order and, therefore, - and the direction of movement of the stepper motor correspond to the counting direction of the reversible counter 1.6.,

Thus, the following mode of operation of the stepper drive is realized. Elements 13, 15, and 19 are used to set the stepper motor controller to its initial state when power is turned on. The key block, together with the delay element 13, ensures that the stepper drive is switched off during the transition process.

The reset is as follows.

When the power is turned on for a time determined by the delay element 13, logical 1 is held at the output of the inverter 15, logical 6 is also held at the third input of the element 6, and high frequency pulses are sent to the inputs of counter 16. The counter 16 with the blink rate is reset to the initial state determined by the source 2 of the reference voltage. After that, the output of the delay element 13 is set to logical 1, the output of the inverter 15, the logical O keys of the block 19 are clamped and the stepping drive is connected to the device, which has been reset to a given time. In the case of the pulse control number, the control inputs of the device are the first inputs of the elements 4 and 5.

Claims (1)

Invention Formula A device for controlling a stepper drive containing a decoder. block of power amplifiers by the number of phases of a stepper motor, pulse generator, first, second and third elements And, a reversible counter, the first and second inputs of which are connected to the outputs of the first and second elements And, respectively, the outputs of the reverse bits of the reverse counter are connected to the inputs of the decoder, outputs power amplifiers are outputs of the device, which is so that, in order to expand the functionality of the device for controlling the stepper drive, a block of keys, digital new converter, IK-trigger, first, second and third elements OR, first and second inverters, delay element, frequency divider, reference source, amplifier-adder and threshold element, the first and second outputs of which are connected to the first inputs of the first and second respectively The second element AND through the first element OR to the first input of the third element AND to the input of the first inverter and the 1 input 1K-flip-flop, the inverse output of which is connected to the first input of the second OR element, the output of which is connected to the third input And element, the second input of which is connected to the output of the pulse generator, C - input of 1K-flip-flop and input of frequency divider, zero input of which is connected to the output of the inverter and K-input of 1K-flip-flop, and the second input of the second element OR is connected to the output of the second inverter whose input is connected via a delay element to the power bus and directly to the control input of the key block, whose outputs are connected to the inputs of the power amplifier block, and the inputs to the outputs of the decoder, the outputs of the frequency splitter and the third element connected respectively with the first and second inputs of the third OR element, the output of which is connected to the second inputs of the first and second elements AND, the third inputs of which are connected respectively to the inverse outputs of the forward and reverse transfers of the reversible counter, the bit outputs of which are connected to the first input through the digital-to-analog converter the amplifier is a suppressor, the second input of which is the input of the device. 513159416 the third input of the amplifier is a voltage coupler, and the output from the input is the same as the output source of the reference booster.