SU1314471A1 - Device for synchronizing with respect to group signal in multichannel communication systems - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity. The synchronization device contains ADC 1, registers 2 and 3, D / A converter 4, frequency divider 5, generator 6 signals of Walsh reference functions, block of active filters 7, processing unit 8 of the error signal consisting of keys 12 and rectifying the analyzer 9 mismatch signal, consisting of adders 14 and 15, voltage dividers 16 and 17, subtractors 18 and quadrants 19, as well as a decisive block 10 and specifying Gd 11. After receiving each from; the input group signal, the synchronization device measures em value of synchronization detuning. As soon as at the output of the analyzer 9 the error signal (the value of the variance of the modules of the output effects of the mutual correlation block of active filters 7) becomes equal to zero, the output of the synchronization device is a frame synchronization pulse, which is extracted directly from the information signal. The goal is achieved by introducing the A / D converters 1, registers 2 and 3, and D / A converters 4, as well as by performing the analyzer 9. 2 Il. S (L with 4 4

Description

eleven

The invention relates to telecommunications and can be used to synchronize multi-channel data transmission systems using the Walsh function.

The aim of the invention is to improve noise immunity.

FIG. 1 is a block diagram of a block signal synchronization circuit in multi-channel communication systems; in fig. 2 - time diagrams for the device operation.

The group signal synchronization device in multi-channel communication systems contains an analog-to-digital converter (ADC) 1, first and second registers 2 and 3, a digital-to-analog converter (HDAP) 4, a frequency divider 5, a generator of 6 Walsh reference function signals, block 7 active filters, the error signal processing unit 8, the error signal analyzer 9, the decisive unit 10 and the master oscillator 11, while the keys and rectifiers are included in the error signal processing unit 8, and the error analyzer 9 The first and second adders 14 and 15, the first and second voltage dividers 16 and 17, blocks 18, -18g, subtractions and quadrants 19, -19f, o | . ... . -. .

The group signal synchronization device in multichannel communication systems operates as follows (in the same way.

Consider the operation of the device for the case. The input group signal is fed to the input of the A / D converter 1 (Fig. 2 a), where it is digitized. The samples of the group signal in binary code from the outputs of the ADC 1 are fed to the inputs of the first register 2, to the clock input of the sequential input of which the pulse of the end of the cycle (ICC) is fed from the output of the frequency divider 5 (Fig. 2b). Under the action of the first ICC, the first received sample of the group signal will be recorded in the first register 2 (in our case with an amplitude of +3). Therefore, a signal of the form: 30,000,000 will be recorded in the first register 2, which under the action of the same ICC from the first register 2 will be overwritten in the second register 3. The sequence of clock pulses from the output of the master oscillator144712

Pa1 is fed to the control current of the generator 6 of the Walsh reference function signals and to the clock input of the second output register 3. The clock frequency of the pulse is determined by the formula

fr | -. (Hz)

those. during time i /, the master oscillator 11 generates n clock pulses. Under the action of clock pulses, the co-clock of the second register 3 enters the information input of the block 7 active filters, previously converted to the original analog form in the DAC 4. In the generator 6, the signals are generated Walsh functions, which arrive at the control inputs of block 7 of active filters, in which the calculation of the cross-correlation functions (PVC) between the input group signal (in this case, the signal of the form 30000000) and n-1 s drove Walsh functions.

After the end of the first integration cycle, the second ICC appears at the corresponding output of the frequency divider 5. Under the action of the second ICC, the second received counting of the input group signal with amplitude -1 is written to the first register 2, and the signal - 13000000 is transferred to the second register 3. In addition, the ICC enters the control input of the error signal processing unit 8, where it opens keys 1 2 1. and voltages proportional to the values of FVK, -FVC, from the outputs of the block 7 active filters are fed to the inputs of rectifiers 13, -13 ". In the error signal analyzer 9, the dispersion of the FVC modules is calculated in accordance with the formula

 ).

where is m

L-1

  one

- the expectation of the modules of the effects X of the block 7 active filters;

 j S (t) (t) dc,, 2n-1;

t.

S (t) - input-multilevel group signal; (t) - Walsh basis functions.

The voltages from the rectifier outputs are summed in the first adder 14, normalized in the first voltage divider 16, and subtracted in the subtraction blocks. Then, the received voltages are squared quadratures and summed in the second adder. 15, after which they are normalized again by the second voltage divider 17 and the variance value of the output effects module 7 active filters is fed to the output of the error signal analyzer 9. The voltage proportional to the value of the dispersion (Fig. 26) from the output of the error signal analyzer 9 is fed to the input of the decision block 10, which is a threshold block, made in the form of

comparator on zero. If the voltage

proportional to the value of the variance will be greater than the threshold voltage of the decision block 10, the logical O remains at its output,

The second integration cycle begins. The sequence of clock pulses from the output of the master oscillator 11 is fed to the control input of the generator 6 and to the clock input of the serial output of the second register-35 (Fig. 2 g). Mismatch signal

3, under the action of which the contents of the second register 3 (a signal of the type 0000003-1) is fed to the information input of the block 7 of active filters, to the control inputs of which the Walsh reference functions arrive. In block 7 of the active filters, the calculation of PVCs, -FVCs ,, ,,.

After the end of the second cycle and the integration of the third ICC into the first register 2, the third received sample of the input group signal is recorded with amplitude -I, and the signal -1-1300000 is overwritten into the second register 3. In block 8, the keys and values are opened FVK, .- FVK, from the outputs of block 1 of the active filters are fed to the inputs of rectifiers 13 ,, -13. In the error signal analyzer 9, the dispersion of the FVC modules is calculated and in the case of exceeding the voltage of the dispersion of the threshold voltage

the decision block does not respond to it again. The third integration cycle begins. The sequence of clock pulses from the output of the master oscillator 11 is fed to the control input of the generator 6 and to the clock input of the serial output of the second register 3. Under the action of the clock pulses, the contents

0 second register 3 (signal type

000003-1-1) is fed to the information input of the block 7 of active filters, to the control inputs of which the Walsh reference functions come from the outputs

5 generator 6. In block 7 active

Filters is another calculation of PVC, -FVK.

After the end of the third integration cycle in the first and second registers 2 and 3, under the action of the fourth ICC, a signal of the type 3-1-1,20000 will be recorded, the dispersion value of which is such (Fig. 26) that the output of the decision unit 10 will be a logical

A synchronization device measures the amount of synchronization detuning after receiving each sample of the input group signal. As soon as the error signal at the output of the error signal analyzer 9 becomes zero, a frame synchronization pulse appears at the output of the synchronization device.

0

five

five

0

is the value of the variance of the moduli of the output effects of the PVC of the active filter block 7, i.e. the frame alignment signal is extracted directly from the information signal.

Claims (1)

Invention Formula A group signal synchronization device in multichannel communication systems containing serially connected active filter units, to the control inputs of which the output of the master oscillator is connected via the Walsh support function signal generator, the error signal processing unit, the error signal analyzer and the decider unit, and the master oscillator output Connected to the input of the frequency divider, characterized by the fact that, in order to increase noise immunity, serially connected analog-digits are entered The converter and the first register, the outputs of the bits of which through the second register are connected to the corresponding inputs of the digital-to-analog converter, and the error signal analyzer is designed as serially connected first adder and first voltage divider whose output is connected to the first combined inputs of the subtractors, the second inputs of which combined with the corresponding inputs of the first adder, and the outputs of the n subtraction units through the corresponding quadra tubes connected to the corresponding input am of the first adder, output is the composer V. Evdokimova Editor M. Bandura Tehred M. Khodanich Proofreader S. Lyzhov Order 2221/56 Circulation 639Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 The second is connected to the input of the second voltage divider, the inputs of the first adder are the inputs and the output of the second voltage divider is the output of the error signal analyzer, while the output of the master oscillator is connected to the clock input of the serial output of the second register, the output of the frequency divider is connected to the write inputs the first and second registers and to the control input of the error signal processing unit, and the output of the digital-to-analog converter is connected to the information input of the active filter unit .