SU1312741A1 - Digital-to-shaft turn angle converter - Google Patents

Abstract

The invention relates to automation and computing and can be used to communicate a digital computing device with actuators. In order to extend the range of operation to a converter containing a generator of linearly varying code, the first 2 is a digital adder, the first N 4, the second 5, the third 6 and the fourth 7 memory blocks, the first 8, the second 9, the third 10 and the fourth 11 digital-analog beef transducers (D / A converters), the first sine-cosine rotating transformer (SQFT) 13, reference element 15, servo amplifier 17, actuator 18 and reference voltage source 19, a second digital adder 3, a demodulator 12, a second SCDT 14 and a block H 6 matching counts. The low and high bits of the input code of the N converter are connected to other groups of inputs of digital adders 2 and 3, respectively. SKVT 13 and 14 operate in the phase shifter mode. Blocks 14, 12, 16, 17, and 18 form a phase-following angle mining system in coarse readout. Blocks 13, 10, 11, 15, 16, 17, and 18 form the phase following i SL with ND -vj 4

Description

angle mining system in accurate readout. The mismatch signal switching of the coarse and exact systems to the input of the servo amplifier 17 is performed by block 16. In the exact channel of the converter, the error from

one

The invention relates to automation and computing and can be used to communicate a digital computing device with actuators.

The aim of the invention is to expand the range of operation of the converter.

The drawing shows a block diagram of the converter.

The converter contains a generator of 1 linearly varying code, the first 2 and second 3 digital adders, the first 4, the second 5, the third 6 and the fourth 7 memory blocks, the first 8, the second 9, the third 10 and the fourth 11 digital-to-analog converters (DAC) the torus 12, the first 13 and the second 14 sine-cosine rotating transformers (SCWT), the comparison element 15, the sample matching unit 16, the servo amplifier 17, the actuator 18 and the source 19 of the reference voltage,

The low and high bits of the input code N of the converter are connected to other input groups of digital adders 2 and 3, respectively

The Converter operates as follows.

The linearly varying code generator 1 generates a binary equivalent of the instantaneous angle u) t, which in blocks 4 and 5 of the memory is converted into the function codes sinwt and cosu, and in the DAC 8 and 9 - into the excitation voltage of ACFR 13 and 14 (WT-100 ) - Vg sinwt and cosujt, respectively, which in this case operate in the phase shifter mode and induce phase-modulated voltages on their rotor windings.

The output voltage of the ACS 14 of the form and cos (U) t + d) is fed to analog inequalities in amplitude and non-orthogonality of the excitation voltages of SCRT 13, non-orthogonality of the digital signals of blocks 6, 7, inequalities of the transmission coefficients of 13

the relay input of the relay demodulator 12, and the control input of it receives a rectangular voltage of the form of sin sin (ix) t + NC), which is formed

in the last digit of the digital adder 3. After straightening and smoothing the low-pass filter included in the demodulator 12, the output voltage of the demodulator 12 is connected by the sample matching unit 16 to the input of the servo amplifier 17 and then, after amplification, acts on the actuator 18 with such so that by turning the rotor

FCS 13 at an angle d reduce the output voltage of the demodulator 12 to zero. In this case, the equality (5t s N (. Up to the unit of the lower digit of the digital adder 3 of the coarse

countdown. It is to this that the role of the phase tracking coarse reference system formed by blocks 14, 12,

16,17, 18 and 14,

After the output voltage of the demodulator 12 has decreased to zero, the sample matching unit 16 connects to the input of the servo amplifier 17 the output of the comparison element I5 and the exact phase tracking system (FSS), formed by blocks 13, 10, is turned on 11, 15, 16,

17,18 and 13.

The FAC-modulated output voltages of the SCVT 13 of the form Ut sin (s t + VK) and Uj cos (tot) where K is the electrical reduction coefficient of the SCWT 13, are fed to analog

inputs DAC 10 and P. After multiplying in DAC 10 and 11 by mutually orthogonal functions and subtracting, the output of the comparison element 15 forms a voltage

Bbu

15

 -Hliy sinCol.-Nj

I3127a14

Claims (1)

Invention Formula W-l 2 sin (2i /) t + 0 / C + N). (I) This voltage contains a constant component proportional to the difference of the voltage specified by the input code N | and spent with (executive element 18, and a variable double frequency component, which is suppressed by a low-pass filter included in the comparison element 15. An accurate count FSS by turning the rotor of SCRT 13 zeroes the voltage of the comparison element 15, which leads to to equality o (and N with an accuracy of one of the least significant bit of digital phase shifters 2, 6, 11 or 2, 7, 10 regardless of and or u2) Analysis of expression (1) shows that the inequality of excitation voltages of SCRT 13, its transformation ratios and transfer ratios of the DAC 10 and 11 does not lead to conversion error. The non-orthogonality of the excitation voltages of the SCWT 13, the non-orthogonality of its rotor and stater windings, the non-orthogonality of the functions sin (u) t + + Nj) and cos (+ N.) of digital phase shifters leads to an error of type zero shift, i.e. not dependent on the angle of rotation of the shaft, which is compensated for by the initial exhibition SCWT 13. The only non-compensable source of heat in this converter is the display error of the sinus ACST, which determines the achievable accuracy of the conversion. Temperature variations cause a zero offset, which is eliminated by thermal compensation. Thus, the instrumental error of conversion in the proposed converter is determined only by the accuracy class of the SCRT of the exact reference used and, as shown by experimental studies, for the case of VT-100 class 0.3, the instrumental error of converting the code to the angle of rotation of the shaft does not exceed 10, which corresponds to the information binary bit capacities ) 0 (five 0 five 0 five 0 five 0 five A code converter into a shaft rotation angle containing a generator of a linearly varying code, the outputs of which are connected to one group of inputs of the first digital adder, the outputs of the first and second memory blocks are connected to the digital inputs of the first and second digital-analog converters, whose analog inputs are connected with the output of the reference voltage source, and the outputs are connected to the first and second windings of the first sine-cosine rotating transformer, the shaft of which is kinematically connected to the shaft The third element and the fourth winding are connected to the analog inputs of the third and fourth digital to analog converters, another group of inputs of the first digital adder is one group of inputs of the converter, the third and fourth blocks of memory, the outputs of which are connected to digital inputs the third and fourth digital-analogue converters, respectively, the outputs of which are connected to the inputs of the comparison element, the servo amplifier whose output is connected to the input of the executive element In order to expand the operating range of the converter, a second digital adder, a second sine-cosine rotating transformer, a demodulator and a sample matching unit, a shaft of the first sine-cosine rotating transformer are kinematically connected to the shaft. The second sine-cosine rotating transformer, the first and second windings of which are connected to the outputs of the first and second digital-to-analog converters, respectively, and a third winding is connected to the first input d A modulator, the outputs of the generator of a linearly varying code are connected to one group of inputs of the second digital adder, the other group of inputs of which is another group of inputs of the converter, and the output is connected to the second input of the demodulator, the outputs of the demodulator and the reference element are connected to the inputs of the sample matching unit . the output of which is connected to the input 513127416 the amplifier, the outputs of the memory generator, and the outputs of the first digital-varying code of the connection accumulator. Connected to the inputs are inputs to the inputs of the first and second block and fourth memory blocks.