SU1305876A1 - Device for majority decoding in case of triple repetition of code combination - Google Patents

Abstract

The invention relates to computing. Its use in the construction of data exchange systems makes it possible to increase the reliability of decoding and expand the scope of application by providing the ability to decode linear codes. The device comprises a quality detector 1, a decoder 4, a switch 5, memory blocks 6 and 7, a majority element 8 and a synchronization block 9. The introduction of correction block 2 and shift register 3 provides correction based on the character quality data prior to decoding, and the input code may not necessarily be cyclical, as in the prototype. 1 hp ff, 4 ill., 1 tab. "With If WITH about SL 00 about :,

Description

The invention relates to computing and can be used in the construction of data exchange systems using linear codes. The purpose of the invention is to improve the decoding confidence and the extension of the field of application by allowing the decoding of linear codes.

Figure 1 shows a block diagram of a device for majority decoding with a three-fold repetition of a code combination; figure 2 - block correction; 3 and 4 are the timing diagrams of the synchronization unit and the correction unit.

The device comprises a quality detector 1, correction unit 2, shift register 3, decoder 4, switch 5, first 6 and second 7 memory blocks, majority element 8 and synchronization unit 9. In FIG. 1, information input 10, first 11 and second 12 setup inputs, clock input 13 and output i 4 are indicated,

The quality detector 1 is designed to analyze the quality of each received (up to n inclusive) code combination symbol and generate an erase signal (b) if the received symbol cannot be identified with 1 or O.

Block 2 correction (figure 2) can be performed on the element 15 BANGE elements AND 16 and 17 and the element OR 18 The shift register 3 has n bits where n is the number of characters of the code combination.

The decoder 4 is designed to detect and, if possible, correct errors in a message encoded with a linear code. A specific type of code determines the execution of decoder 4.

Switch 5 can be performed on three AND elements, the first inputs of which are combined and are informational, and the second inputs are the corresponding control inputs of switch 5,

The first memory block 6 is designed to fill in the decoding results (the presence or absence of errors in the code pattern).

The second memory block 7 contains three registers (R 1, R 2 and R 3) with a capacity of K characters each, where K is the number of information symbols of the code word. This block 7 is intended

for storing information symbols of a three-code message code vector,

The majority element 8 can work in two modes: voting by majority or choosing one of three combinations. The operation mode of the element 8 is provided with control signals from block 6.

The synchronization unit 9 provides the clock pulses to the device blocks in accordance with the time diagram of FIG. 3, where it is indicated: a - input signal (input 10); GfB - signals on the first and second setup inputs 11 and 12 (There is a marker after the timeout and there is a marker) - g - clock synchronization pulses; dk - signals on the second - the seventh outputs of block 9.

The signal at the first output of the synchronization unit 9 repeats the signal at the first setup input P (Fig. 3b). The device for the majority decoding of cyclic codes with a threefold repetition of the code combination works as follows.

The initial state is provided by the sync pulse from the first output of block 9 (Fig. 3b). This pulse allows zeroing all the memory elements of the device and allows the passage of clock synchronization pulses (Fig. 3g), demarcated per bursts of a certain length, to the sync inputs device blocks.

The symbols of the first repetition of the code combination with the pulse frequency from the second output of block 9 (Fig. 3D) enter decoder 4 and correction block 2, from the output of which they are written to shift register 3. From the output of the 4K decoder, the information symbols through the switch 5 are entered in block 7 (in the register R 1) in sync pulses from the third output of block 9 (Fig. Ze). At the same time, the analysis from dividing the code combination by the forming polynomial is entered into block 6 by signals from the sixth output of block 9 (Figs. 3i). Correction unit 2 is designed to correct symbols in received codewords using an erase signal for this signal that carries information about the quality of the received symbol. The principle of correction is as follows. When receiving the first repetition, it is stored in shift register 3 (Y). When receiving a second repetition (i, the corresponding erasures are fixed in it and the result of adding modulo two () of the same-named symbols is determined by the result of HQ e-VN.

Dovy vectors and

The one multiplying it with a certain probability will point to the distorted second repetition symbols, which are inverted according to e. The corrected combination will look like).

LTD

about

about about 1

I

oh oh

Based on the table, it is possible to draw up an algorithm for the operation of the correction block 2: if the erase signal is present (0 1), then preference is given to the previously received (better) symbol; if the erase signal is absent (0), the character of the received combination is entered into register 3.

Each decoded repetition of a code combination from decoder 4 is recorded in block 7 in its own register, and in block 6 the remainder of dividing this repetition by the forming polynomial is written.

Thus, after receiving three repetitions of a code combination, the memory block of information symbols is stored in memory block 7, and in block 6, information about errors detected in these repetitions is stored.

From the beginning of the sync pulse packet (Fig. 3k), information from the outputs of the registers 7 enters the inputs of the majority element 8, the operating modes

(Fig. 4) allow the correction of a certain proportion of errors in the second repetition of the message. The corrected combination is entered into the shift register 3 and when the third repetition is received, the described operations are repeated, with the information stored in register 3 acting as Y, and being received from input 10 as 2.

Possible combinations of 2 and error correction are shown in the table.

about 1

about 1

about i

about about about 1

about 1

oh oh

about about 1

oh oh

five

0

five

.

which are given by signals that are connected to the control inputs of element 8 from the outputs of block 6.

The first mode of operation. If decoder 4 did not detect errors in all three received codewords or detected an error in only one of them or in all three code combinations, then at the output of the dominant element 8 binary symbols will be the result of voting on the majority of the same positions all reps.

The second mode of operation. If decoder 4 detected errors in two code combinations, then at the output of the majority element 8 there are characters in the TC in the same combination in which no errors were detected.

In accordance with the selected mode, the element 8 generates the final processing result at the output.

Thus, in the proposed device, error correction based on the character quality data is carried out before decoding, in contrast to the known device, where this correction was made already after decoding. In this case, in a known device, a situation is possible, when one of the combinations was transformed under the influence of interference in the communication channel so that it was received as crimped (the decoder did not detect an error), and in the other two combinations errors were detected. Then, at the output of a known device after the termination of reception in TC, the symbols of a deliberately false combination (the majority element works in the second mode), Although its symbols are after decoding and are corrected based on the quality of received symbols, however, the probability that not all errors of the combination will be corrected, but only a part of them.

Thus, at the output of the known device, the information is corrupted. In the proposed device, even if not all errors are corrected, but only a part of them, decoder 4 will detect these errors. Therefore, the majority element 8 will operate in the first mode, i.e. The symbols at the output of the device will be the majority voting results. And since the interference in the communication channel is a random process, it affects various symbols of different repeats. Therefore, the result of majority voting (voting) will be devoid of technical errors that would exist in a known device. In addition, information coming from a communication channel can be encoded not only with a cyclic code, but with any linear code.

Claims (2)

Invention Formula i. A device for majority decoding with a threefold repetition of a code combination containing a quality detector, the information input of which is the information input of the device, the decoder, the first and second outputs of which are connected to the information inputs of the first memory block and the switch, respectively. the informational inputs of the second memory block, the major element And the synchronization block, the first output of which is connected to the first control inputs of the quality detector, the decoder of the memory blocks, the second output is connected to the second control inputs of the quality detector and the decoder, the third, fourth and fifth outputs of the synchronization unit are connected to the first, second and third control respectively the switch inputs and to the second, third and fourth control, it inputs to the second memory block, the sixth output of the synchronization block is connected to the second control; it to the input of the first memory block, the outputs of which are connected to the first information inputs of the majority element, the seventh output of the synchronization block is connected to the control input of the majority element and the fifth control input of the second memory block, the outputs of which are connected to the corresponding second information inputs of the majority element, the output of which is the output of the device, the first, second and the third inputs of the synchronization unit are respectively the first and second setting and clock inputs of the device, characterized in that, for the purpose of turning, For decoding and expanding the scope of application, by enabling the decoding of linear codes, a shift register and a correction block are entered into the device, the first and second information inputs of which are connected to the corresponding outputs of the quality detector, the output of the correction block connected to the information inputs of the decoder and the shift register whose output connected to the third information input of the correction unit, the first and second control inputs of the shift register and the control input of the correction unit are connected respectively to the first, second, and third outputs of the sync block. 2. The device according to claim 1, that is, that the correction block is made on the first and second elements AND, the C / SHRET element and the OR element, the output of the AND elements and the BANE element are connected to the inputs an OR element whose output is a block output, allowing the entry of a BAN member is the first information input block the input of the BAN element and the first input of the first element AND are combined and are the second information input of the block, the first input of the second element And is the control input of the block, the second And elements are combined and are the third information input of the block. Fie.2 Compiled by O. Revinsky Editor A. Shandor Tehred V. Kadar l: l ° l: L Sign up 466/56 Circulation 902 VNIIPI State Committee LCLt for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production printing company, Uzhgorod, Projecto st., 4 Fiz. Subscription