SU1302300A1 - Device for calculating amplitude histograms of television pictures - Google Patents

Abstract

The invention relates to computing and can be applied in technical vision systems of industrial robots. The aim of the invention is to enhance the functionality by providing image processing in individual parts. The device contains a clock pulse generator 1, a block of 2 counters of the number of elements and lines, a synchronization block 3, an analog-digital converter 4, a multiplexer 5 coordinates, a data multiplexer 6, a write-read multiplex 8, an input-output block 9, a trunk 10, a block 11 memory adder 12. 1 hp f-ly, 3 ill. Q 3 cl FM1

Description

The invention relates to computing and can be used in solving image recognition problems and in technical vision systems of industrial robots.

The aim of the invention is to expand the functionality of the device by providing image processing on individual fragments.

Figure 1 presents the scheme of the proposed device; figure 2 - diagram of the synchronization unit; on fig.Z - timing diagram of the synchronization unit.

The device contains a generator of 1 pulse, a block of 2 counters of the number of elements and lines, a block of 3 synchronization, the analog-digital conversion of which is determined based on the conditions of the problem being solved.

Before starting the calculations, all multiplexers 5-8 through block 9 with help

5 external controlled device of the system (computer or microprocessor) is transferred to the reception of information, after which the entire memory area of block 11 is reset by successively searching through the addresses of all its cells through multiplexers 5 and 7 with simultaneous input of a recording signal through multiplexer 8 at zero input data transmitted through

 5 multiplexer 6. Then the multiplexer is switched to receive mode information from the internal channels of the device.

The start of the calculation is followed by

the caller (ADC) 4, multiplexer 5 by presetting the corresponding signal transmitted from one of the outputs of block 9 to the input of the counting solution of block 3 (trigger inputs 15 and 16, Fig. 2). The appearance of this

ordinate, data multiplexer, address multiplexer 7, write-read multiplexer 8, input / output unit 9, trunk 10, memory block 11, adder 12, element 13, element | NOT 14, triggers 15 and 16, element 17 delays and element 18. In FIG. 3A - the output of the element 13, B - the output of the element 17, C - the output of the element 18.

 The device works as follows.

OXK pulse 30 during counting resolution does not change the state of flip-flops 15 and 16, therefore the Select chip signal (VC) at the output of element 13, formed by a logical combination of out-of-unit 2, clocked by generator 1, generates a set of control signals for the external 35 Dov of these triggers, a signal from the PCS and a television sensor, part of the clocking pulse (TI), are used by the synchronization unit 3. The video signal of the image obtained using this sensor, configured to control unit 11, is still absent. There is also no signal at the output of element 18, given to the input of ADC 4, which, also 40 which, together with the VC signal and forms clockwise by generator 1, produces the output of block 3. The signals at the output, this is the discretization of the video signal, over time passing and quantizing it in amplitude, the pre-falling edge of the first OCC pulse, put the luminance values in each when the output of the trigger 15 by setting the image point parallel is digitized 45 into one position (zero code arriving at one of the preceding The output of the trigger 16 with the two inputs of the multiplexer 7. It does not change with its help and its inverse multiplexer 7 selects the output to allow the counting). After the address is the addressing of the cells inside the individual during the entire time of the direct memory areas of block 11, then 50 of the frame’s stroke (except for

return line) clocking pulses pass to the output of block 3 and periodically reveal the contents of block 11 of memory through the multipliers in the row and the counter of the number of rows, 55 lexor 8 at the address transmitted from which this block is organized. cut multiplexer 7 from the output of the ADC 4 and

through the multiplexer 5 from the output of block 2. At each subsequent treatment, the contents of the expanded cells of block 11

the time as the source of the address of these areas themselves is chosen by the multiplexer 5. The output at block 2 is formed by a group of higher bits of the counter number Elementary bits allow to obtain a large-scale coordinate grid on the field of a television frame, the format

which determines the outcome of the conditions of the problem being solved.

Before starting the calculations, all multiplexers 5-8 through block 9 with the help

the external controlled device of the system (computer or microprocessor) is transferred to receive information, after which the entire memory area of block 11 is reset by sequentially iterating over the addresses of all its cells through multiplexers 5 and 7 with simultaneous input of a recording signal through multiplexer 8 at zero input data transmitted via

multiplexer 6. Then the multiplexers are switched to the mode of receiving information from the internal channels of the device.

The start of the calculation is followed by

a twist signal transmitted from one of the outputs of block 9 to the input of the resolution of the block 3 (trigger inputs 15 and 16, FIG. 2). The appearance of this

the signal removes blocking from triggers clocked by the frame reverse signal (OCC), received together with the forward run signal (PHC) from block 2. The leading edge of the first

the OCC pulse during counting resolution does not change the state of the flip-flops 15 and 16, therefore the Select chip signal (VC) at the output of element 13, the scans of these flip-flops, the PHC signal and the clocking pulse (TI)

called the logical combination of the outputs of these triggers, the PHC signal and the clocking pulse (TI), designed to

using the adder 12 is incremented by one and fed through multiplexer 6 again to the input of block 11 is recorded at the same address by the recording signal from the output of block 3 through multiplexer 8. This continues until the second OCC pulse at the input of block 3 overturns trigger 16, which prohibits further calculation (the output of this trigger can be used as a sign indicating the completion of the calculation and transmitted through block 9).

As a result of repeated execution of the described counting procedure performed during one frame, in block 11 of memory a set of private amplitude histograms is formed, characterizing the brightness of the image under study within separate fragments dividing the frame field into equal parts. These histograms can be programmatically read from block 11 by switching all multiplexers through block 9 to the output. The readout is performed in the same way as pre-zeroing, replacing the write signal with the read signal by an external control device.

To obtain a generalized histogram from the entire frame floor, it is enough not to switch multiplexer 5, which has a separate control input independent of the other multiplexers, from the output of block 9 to the output of block 2, specifying a fixed part of the total address of block 11 in memory during histogram calculation and retaining it during the subsequent linking.

Formula of invention

Claims (2)

1. A device for computing amplitude histograms of television images containing multiplexers of address, data and write-read memory block, unit adder, block of counters of the number of elements and lines, synchronization block, analog-to-digital converter, the output of which is connected to the first information input the address multiplexer, and the input is the information input of the image elements of the device, the output of the address multiplexer is connected to the input of the first field of the address of the memory block, the information input and the write input are tyvani which are respectively connected to outputs of the multiplexer d-data and read-write multiplexer, the output of the memory unit is connected. to the output of the device and to the input of the adder unit, the output of which is connected to the first information input of the data multiplexer, the second information input of which is the input of the initial data installation of the device, the second information input of the address multiplexer and the first information input of the read / write multiplexer and the data write-read control input of the device, the control inputs of the address, data and write-read multiplexers are connected to the mode reference input The initial setup-computation device, the sync block trigger input is the trigger for computing the device, the second information input of the write-and-read multiplexer is connected to the sync block output, the first and second inputs of which are connected to the first and second sync outputs of the counters block of the number of elements and lines , the third input of the synchronization block, the clock inputs of the block of the counters of the number of elements and lines and the analog-digital converter are connected to the output of the clock generator, differing Just because, in order to expand the functionality by providing image processing on individual fragments, a coordinate multiplexer is inputted into it, the output of which is connected to the input of the second address field of the memory unit, the first information and control inputs of the coordinate multiplexer are the second input of the installation the address and the input of the device calculation modes, respectively, the second information input of the coordinate multiplexer is connected to the output of the coordinate values of the fragments of the image of the account block tchikov number of elements and lines. 2. The device pop. 1, which differs from the fact that the synchronization unit contains AND elements, NOT elements, delays and two triggers, the first and second inputs of the first AND element being the third and first inputs of the block, respectively; and the sync input of the first trigger is connected to the second input of the block, the third and fourth inputs of the first element I are connected to the direct output the second and inverse inputs of the first flip-flops, respectively; synchronization of the second flip-flop is connected to the output of the element NOT; the setup inputs of the first and second flip-flops are connected to the input of the block count resolution, the information input of the first ./7HS / L ov 13023006 the trigger is connected to the direct input of the second trigger, the output of the first element AND is connected to the first input of the second element AND and through the delay element to the second input of the second element And, the outputs of the first and second elements And are the output of the block. / 7 18  P t f Yu Phys .2 Editor I.Nikolaychuk Compiled by A. Zherenov Tehred A. Kravchuk Proofreader A.Zimokosov Order 1218/49 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 Fi.3