SU1300607A1 - Stabilized converter - Google Patents

Abstract

The invention relates to converter equipment and can be used in secondary power sources. The purpose of the invention is to increase the range and linearity of the output voltage regulation. The converter contains an inverter 1 with transistors 2-5, a power transformer 6, a protection circuit 7 against through currents, a load 8, a rectifier with a filter 9, a feedback amplifier 10, a modulator 11, a sawtooth generator 12, a master oscillator 14 , division) -frequency 13, power amplifier 26. The sawtooth voltage generator 12 is designed as a triangular voltage source and a logic block 16 is inserted, made on circuits AND 15, 17, triggers. 18, 19 circuits OR 20-23, and RS-flip-flops 24 and 25 and a forced control circuit on the elements And 27, 28 and the element OR 29. Management provides full regulation; phase angle from 0 to 180 ° with the linearity of the adjustment characteristic and the presence of control pulses of transistors 2-5 in all modes of operation. The invention improves the reliability and quality of power with changes in input voltage. 2 Il. About

Description

) 0

11300607

The invention relates to educational technology and can be used in various electronic equipment and automation devices, in particular in power supply systems,

The purpose of the invention is to increase the range and linearity of voltage regulation at the output of the converter.

Figure 1 presents the scheme of the proposed device; in FIG. 2, timing diagrams.

The device contains a controlled transistor inverter i with power transistors 2-5, an output power transformer 6, an end-to-end protection circuit 7, a load 8, a rectifier 9 with a filter, and a feedback amplifier 0 connected to the DC input of the modulator 11, to the modulating input of which the output of the source 12 of a triangular voltage is connected, the input of which is connected to the forward output of the first stage of the frequency divider 13. The input splitter 13 is connected to the output of the master oscillator 14, the direct output of the modulator 11 is connected to the first circuit 15 of the logic block 16, the second input of which is connected to the inverse output of the splitter trigger 13, and the inverse output of the modulator 1 is connected to the first input the second circuit And 17, the second input of which is connected to the direct output of the trigger 13. The forward and inverse outputs of the divider. 13 are connected to clock inputs of counting triggers 18 and 19 of the second stage divider, with direct output

directly to the inputs of an adjacent pair of transistors 2 and 3, and the direct and inverse outputs of trigger 25 through power amplifier 26 and circuits 27 and 28 to another adjacent pair of transistors 5 and 4, the first inputs of circuits 27 and 28 are connected through IPI 29 to the first two outputs of the power amplifier, the auxiliary input of which

connected to the circuit 7 from the pass-through currents, the input of which in turn is connected via voltage sensors to the power transistors 2-5,

The device works in the following 5 ways.

The master oscillator 14 generates a sequence of pulses arriving at the input of the frequency divider 13 (for example, a counting trigger). The signal from the direct trigger output 13 (signal a, fig 2) is fed to the input of the triangular voltage source.

The triangular voltage (V1, V, Fig.2) is compared with the feedback voltage (V) with the help of the modulator P, the output of which generates a sequence of pulses (signals, Fig 2) whose duration depends on the level of the reverse voltage connection.

The direct (signal, fig, 2) and inverse signals from the output of the frequency divider 13 arrive at the counting inputs of the flip-flops 18 and 19 of the frequency divider at the 35-th stage, and the direct output signal of the trigger 18 (signal of the direct output to, fig2) arrives at the D input (trigger delay input 9 (D is a trigger), which allows you to generate 20

25

thirty

the trigger 18 is connected to the input of the delayed response signal of the trigger 19 (the AC signal (D input) of the trigger 19,

The direct and inverse outputs of the trigger 19 are connected to the second inputs of the OR circuit 20 and 21 of the logic unit, the first inputs of which are connected to the output of the AND 15 circuit, the Direct and inverse outputs of the trigger 18 are connected to the second inputs of the OR circuit 22 and 23, the first inputs which are connected to the output of the circuit And 17, the outputs of the circuits OR 20 and 22 are connected to the S-inputs of the RS flip-flops 24 and 25, the outputs of the circuits 21 and 23 are connected to the R-inputs of the same flip-flops.

The outputs of the flip-flops 24 and 25 through the power amplifier 26 are connected to the inputs of the power transistors 2-5, and the direct and inverse outputs of the trigger 24 are connected directly

of the output, FIG. 2), shifted by 90 relative to the analogous signal of the trigger 18, the output signals of the modulator 11 and the triggers 18 and 19 are sent to the logic block 16 containing two AND schemes (-15 and .17) and four OR schemes ( 20-23)

The output signals of the circuit AND 15 (signal e), .circuit AND 17 (circuit f), the circuit OR 20-23 (signals U Uj.) Are shown in figure 2.

The output signals U - Ug of the logic block 16 are fed to the R- and S-inputs of the trigger 55 and 24 and 25, The output signals of the flip-flops 24 and 25 (the signals Q, Q4 from the direct outputs are shown in the flat line in FIG. 2, and Qj, Qs (dashed line) correspond to output signals

directly to the inputs of an adjacent pair of transistors 2 and 3, and the direct and inverse outputs of trigger 25 through power amplifier 26 and circuits 27 and 28 to another adjacent pair of transistors 5 and 4, the first inputs of circuits 27 and 28 are connected through IPI 29 to the first two outputs of the power amplifier, the auxiliary input of which

connected to the circuit 7 from the pass-through currents, the input of which in turn is connected via voltage sensors to the power transistors 2-5,

The device works as follows.

The master oscillator 14 generates a sequence of pulses arriving at the input of the frequency divider 13 (for example, a counting trigger). The signal from the direct trigger output 13 (signal a, fig 2) is fed to the input of the triangular voltage source.

The triangular voltage (V1, V, Fig.2) is compared with the feedback voltage (V) with the help of the modulator P, the output of which generates a sequence of pulses (signals, Fig 2) whose duration depends on the level of the reverse voltage connection.

The direct (signal, fig, 2) and inverse signals from the output of the frequency divider 13 are fed to the counting inputs of the flip-flops 18 and 19 of the second frequency divider, and the direct output signal of the trigger 18 (the direct output signal to Fig.2) to the D input (trigger delay input 9 (D is a trigger), which allows you to generate

of the output, FIG. 2), shifted by 90 relative to the analogous signal of the trigger 18, the output signals of the modulator 11 and the triggers 18 and 19 are sent to the logic block 16 containing two AND schemes (-15 and .17) and four OR schemes ( 20-23)

mustache: or 1 ate 2b power 1kstn, but without taking into account the work 1 protection against through currents,

Dp of elimination of additional losses in the inverter transistors due to leakage currents apply the fixed and automatic delay circuit of the next transistor.

The output of the overcurrent protection circuit 7 is connected to the blocking inputs of the power amplifier 26, and the input through the transistor state sensors to the power transistors 2-5 of inverter 1, the circuit cuts out the output of the control pulse to the next inverter power transistor only after turning off the previous transistor. Thus, the control pulses of an adjacent pair of power transistors will be shifted from one another, by an interval determined by the eight turn-off time of the previous transistor. But known schemes do not provide a line. adjustment characteristics due to untimely exit from shunting, and in some cases can lead to failure of the inverter.

At time t (see Fig. 2), transistors 3 and 5 are connected. At time t, a control pulse is removed from transistor 5, but no pulse is sent to transistor 4, since transistor 5 remains in the switched-off state due to resorption of carriers and the load current flows through the transistors 3 and 5.

At time t, after switching off transistor 5, circuit 7 gives permission to supply a control pulse to the input of transistor 4. After turning off transistor 4 (when transistor 3 is on), the load is shorted through these transistors, a pause in the output voltage occurs. At time tj, control is removed.

To eliminate this, the proposed device uses a forced control circuit (AND 27, AND 28, OR 29) by another adjacent pair.

30 transistors 5 and 4 which form the signals P and

Pj (see figure 2) in such a way that they will have additional dips to zero in cops lacking signals P, or

35 RP.

Such control, in the case of reverse load, allows switching off transistor 4 and interrupting the load current through the reverse diode of the transistor.

40 3, which allows for the timely activation of the next valve 2 and, therefore, the exit from the load bypass mode.

The device provides full adjustment of the phase angle from 0 to 180 ° with the linearity of the regulating characteristic and the presence of pulses controlling the inverter power transistors in all modes of its operation.

The invention changes the reliability and power quality of devices with deep changes in input voltage.

with transistor 3, transistor 2 is turned on at time t. If at time t reversal of the load current occurs (a possible cause of the reverse may be a recharge of the load capacitor), then the current flows through transistor 4 (we assume that the current pulse of transistor 4 is long, in Fig. 2 this is shown by a dashed line) and turned on diode of transistor 3. This is perceived by the through-current protection circuit 7 as comprising a controlled bridge inverter Formula of the Invention Stable converter, the sleep state of transistor 3 (despite the fact that in the interval t - s it can be already off condition) and there is a forced delay in the turn-on of transistor 2, and therefore, the output from the load-transfer mode (pause mode).

The adjustment characteristic of an inverter is the dependence of its output voltage on the ratio between the duration of the conductor O 5 0

either f

(t (j) and pauses (t), i.e. U, (y),

c / g "itajf-iui / j 1.5 ;. - etJlX

tu tu.

ty + t; t72

The duration of the load current and pause pulses are determined by the control system depending on the purpose of the control (maintaining the average value of the voltage, or acting, etc.). In the case of a forced delay in exiting the bypass mode, the length of the pause varies arbitrarily and the reduced dependence becomes nonlinear.

To eliminate this, the proposed device uses a forced control circuit (AND 27, AND 28, OR 29) by another adjacent pair.

0 transistors 5 and 4, which form the signals P and

Pj (see figure 2) in such a way that they will have additional dips to zero in cops lacking signals P, or

Rz.

Such control, in the case of reverse load, allows switching off transistor 4 and interrupting the load current through the reverse diode of the transistor.

3, which allows for the timely activation of the next valve 2 and, therefore, the exit from the load shunting mode.

The device provides full control of the phase angle from 0 to 180 ° with the linearity of the regulating characteristic and the presence of pulses controlling the inverter power transistors in all modes of its operation.

The invention changes the reliability and power quality of devices with deep changes in input voltage.

holding controlled bridge inverted controlled bridge inverted formula of the invention Stabilized converter, co5 13

a torus with an output transformer and control unit, including a series-connected master oscillator, a frequency divider, a saw-tooth voltage generator, a modulator and a power amplifier, as well as a rectifier, filter and amplifier (feedback loop, characterized in that , with a circuit for increasing the range and linearity of voltage regulation at the converter output, the sawtooth generator is designed as a source of triangular voltage, a logic block is introduced on two AND and four OR circuits, RS trigger and force a circuit one of the adjacent pairs of power transistors, with the first-stage input of the frequency divider connected to the master

generator, and the output to the input of the source of a triangular voltage, the output of which is connected to one of the inputs of the modulator, the second input of which is connected to the output of the reverse

t5

The frequency bodies are connected to the second inputs 0 of the first OR circuits of the logic unit, the first inputs of which are connected to the output of the second AND circuit, and the output signals of the second trigger of the second stage of the frequency divider are connected to t5 the second inputs of the second OR circuits of the logic unit, the first inputs of which are connected to the output of the first circuit AND, and the outputs of the OR circuit are connected via RS-flip-flops to the inputs of the power amplifier, which with its two outputs is connected to the inputs of one pair of adjacent transistors of the inverter, and the other two to the inputs of another pair adjacent transistors

connections, and direct and inverse outputs of the MO-25 through the circuits And, the second inputs of which

The puller is connected to the first inputs of the logic circuit AND block, the second inputs of which are connected to the direct and inverse outputs of the first stage of the frequency divider, which in turn are connected to the clock inputs of the two second stage trigger, and the second stage of the second trigger of the second stage split is connected to the input of the delay {and the second trigger, and the outputs of the first trigger of the second CTynenvj delhi

The frequency bodies are connected to the second inputs of the first OR circuits of the logic unit, the first inputs of which are connected to the output of the second circuit AND, and the output signals of the second trigger of the second stage of the frequency divider are connected to the second inputs of the second OR circuit of the logic unit, the first inputs of which are connected to the output of the first And, and the outputs of the OR circuits are connected via RS-flip-flops to the inputs of the power amplifier, which with its two outputs is connected to the inputs of one pair of adjacent transistors of the inverter, and the other two to the inputs of another pair with interstitial transistors

through the circuits And, the second inputs of which

connected via the OR circuit to the first two outputs of the power amplifier.

Claims (1)

Claim A stabilized converter comprising a controllable bridge inverter with a transformer at the output and a control unit including a serially driving oscillator, a frequency divider, a sawtooth generator, a j-module and a power amplifier, as well as a rectifier, filter and feedback amplifier, characterized in order to increase the range and linearity of voltage regulation at the converter output, the sawtooth voltage generator is made in the form of a source of triangular voltage, logic lock on two AND circuits and four ORs, RS-flip-flops and 15 forced-control circuit of one of the adjacent pairs of power transistors, the input of the first stage of the frequency divider connected to the master oscillator, and the output to the input of the triangular voltage source, the output of which connected to one of the inputs of the modulator, the second input of which is connected to the output of the feedback amplifier, and the direct and inverse outputs of the modulator are connected to the first inputs of circuits AND logic block, the second inputs of which are connected to the direct and inverse outputs of the first stage of the second divider, and the outputs of the first trigger of the second stage of the frequency divider are connected to the second inputs of the first OR circuits of the block logic, the first inputs of which are connected to the output of the second AND circuit, and the output signals of the second trigger of the second stage of the frequency divider are connected to the second inputs of the second circuits OR logic block, the first inputs the odes of which are connected to the output of the first AND circuit, and the outputs of the OR circuits via RS triggers are connected to the inputs of the power amplifier, which, with its two outputs, is connected directly to the inputs of one pair of adjacent inverter transistors, and the other two to the inputs of another pair of adjacent transistors through AND circuits, the second inputs of which are connected through the OR circuit to the first two outputs of the power amplifier. I 80060 / Fig. 2