SU1292202A1 - Device for detecting amplitude-phase-modulated signals - Google Patents

Abstract

The invention relates to a technique for data transmission over communication channels and provides greater interference with phase jumps. The device contains a group correlator 1, blocks 2, 25 recalculation of signal projections, code converters 3, 4, decisive block 5, block 6 decoding, YH1 D. / M -Hj m-gs-VykOudonih -5 1 R (L

Description

phase mismatch analyzer 7, switches 8, 9-, 16-19, adders 10, 11, 21, 22, operational storage units 12, 13, amplitude, selector 14, elements OR 15, AND 20, 29 33, multipliers 23, 24 , averagers 26, 27, comparison blocks 28.31, trigger 30, shift register 32. In the group correlator 1, the coefficient of correlation of the input group signal with 2 n-support signals is calculated. In decision block 5, they are compared with a threshold. As a result of the comparison, a four-bit binary number is generated, which is decoded into information transmitted over a given channel.

The invention relates to communication technology and can be used to construct coherent high-speed multi-channel MSS receivers.

The purpose of the invention is to increase the noise immunity at phase jumps.

The drawing shows a structural electrical circuit of the proposed device.

The device for detecting amplitude-phase-modulated signals contains the group correlator I, the first block 2 of the signal projection recalculation, the first 3 and second 4 code converters, the retoupler unit 5, the decoding unit 6, the analyzer 7: phase detuning, the first 8 and second 9 switches, the first 10 and second 11 adders, the first 12 and second 13 operational memory block; ki, amplitude selector 14, element OR 15, third 16, fourth 17, five 18 and sixth I9 switches, first element 20, third 21 and quarter 25 adders, first 23 and second 24 multipliers, second block 25 conversion signal projections, the first 26 and the second 27 are delighted, the first comparison unit 28, the second element AND 29, the trigger 30, the second comparison unit 31, the shift register 32, the third element And 33.

mation symbols. Analyzer 7 generates the values of the correction coefficients. for each channel, which are then averaged in a group digital integrator consisting of switches 8.9, adders 10, 11, and memory blocks 12, 13. The values of the coefficients obtained. recalculation through switches 18, 19 is received at block 2. To eliminate false positives of the phase jump compensation circuit in the case of synchronization, a synchronism detector is provided, consisting of a comparison unit 28, a shift register 32 and an AND 33 element.

The device works as follows.

The input group signal S (nt) is fed to the input of the group corrector 1, in which the correlation coefficients Xc and Y (, 2, ..., n) of the input signal with 2 n are calculated using a specific algorithm for each clock interval signals. The resulting coefficients. are converted in the first block 2 by the appropriate algorithm through the first 3 and second 4 converters, the code is sent to the decision block 5, where they are compared with a threshold equal to (l2n |). As a result of the comparison, a four-digit binary number is generated, which is decoded in the decoder 6 into the transmitted on this channel oops information

characters a,

 3 The adjustment of the values of the conversion factors cosQ and sinQj, (k 1,2, ..., p) is carried out by signals from the fifth 18th and sixth 19 switches. The phase mismatch analyzer 7 generates the values of the correction factors.

lh

and uY. (, 2, ..., p) for each channel, which are then averaged in the group digital integrator consisting of the first 8 and second 9 switches, the first 10 and second 11 adders and the first 12

and second 13 storage blocks. The values of cos (f and sin cf (k 1, 2, ..., n)) obtained at the output of the first 12 and second 13 storage blocks through the fifth 18 and sixth 19 switches are switched to the inputs of the first block 2.

Amplitude selector 14 analyzes signals A (generates a signal and, when processing signals with a minimum amplitude (class S (1) and signal Uj, when processing signals with a maximum amplitude (class S (3). Element OR 15 performs the logical addition operation signals U, VUU. The clock signal u2 serves for synchronization with the processed signals A (X, Y |), k 1, n outputs from the first 12 and second 13 storage blocks of the corresponding coefficients sintf, kl, n. In the absence of a phase jump Tpiirrep 30 is in its natural state

ABOUT.

syrup in the first 26 and second 27 averagers. The amplitude of the averaged signal sinM is compared in the second comparison block 31 with the second

5 P, and if it is exceeded by the signal and in the presence of a synchronization signal U | Q, the second element I 29 generates a signal for setting the trigger 30 to the state Log.1.

10 Comparison of the sinder signal with the threshold Pn is intended to reduce the effect of small random phase fluctuations, which are caused by gaums in the channels. 3. The value of the threshold P is selected.

15 within sin 3 - sin 5 °. At the next clock interval by the signal U, the third switch 17 is disconnected - the memory of the previous state is achieved by the first and second mediums 20 strings 26 and 27, and the fifth and sixth switches 18 and 19 switch the output signals from the output of the second projection recalculation unit 25 signal. At the same time, at the next time interval signal Ug from its output at the output, the signals cosCp, and sinqi, k 1, parallels the 18 and sixth 19 switches are additionally converted in the second block 25 in accordance with predetermined algorithms, i.e. phase compensation is performed. With output 30 and p of the 18 and sixth 19 switches, the corrected signals cosqi | and sinq) ,,, k 1, n do ...

The ditch switches their first inputs, and the fourth switch 17 connects the signals to the inputs of the third and fourth adders 21 and 22 when the signals from the S (T) FROM (3) classes are processed. The control signal of the fourth switch 7 is formed: by the first element AND 20, implementing the function U4 L U9. The signals A (X, Y) corresponding to the classes S (1) and S (3) are fed to the inputs of the third 21 and fourth 22 adders. The received signals are scaled by multiplying their amplitudes in the first 23 and second 24 multipliers by the coefficients Qi and o., Which are switched by the third switch 16, depending on the presence of the control signal S, (1) or S (3). The amplitude of the signals Hc and Yj, respectively. signal. R (1), multiplied by the wavelength inputs of the first block 2 and the first inputs of the first 10 and second II sum

j tori. At the end of the X and Y signal processing cycle by the signal Ug, trigger 30 is set to the Log state. O and the device returns to the initial state.

40 To avoid false triggering of a phase jump compensation scheme in cases of synchronization occurrence, a synchronization detector is provided in the proposed device.

45 of the first comparison block 28, the shift register 32 and the third element AND 33.

ficient (xf

and the amplitude of the signals

X and Y |, corresponding to signals from class S (3), are multiplied by o.

The amplitudes of signals X and CCs similarly scaled correspond to the values of the trigonometric functions sinuq), respectively, where Mf uCf + P, L (is the magnitude of the phase jump with an accuracy of +45, and 9 is a disturbance in the OPS channel. The obtained values of cos Atp and sinuCfe are average for

12922024

syrup in the first 26 and second 27 averagers. The amplitude of the averaged signal sinM is compared in the second comparison block 31 with the second

5 P, and if it is exceeded by the signal and in the presence of a synchronization signal U | Q, the second element I 29 generates a signal for setting the trigger 30 to the state Log.1.

10 Comparison of the sinder signal with the threshold Pn is intended to reduce the effect of small random phase fluctuations, which are caused by gaums in the channels. 3. The value of the threshold P is selected.

15 within sin 3 - sin 5 °. At the next clock interval by the signal U, the third switch 17 is disconnected - the memory of the previous state is achieved by the first and second mediums 20 strings 26 and 27, and the fifth and sixth switches 18 and 19 switch the output signals from the output of the second projection recalculation unit 25 signal. At the same time, at the next clock intern the inputs of the first block 2 and the first inputs of the first 10 and second II sum

tori. At the end of the X and Y signal processing cycle by the signal Ug, trigger 30 is set to the Log state. O and the device returns to the initial state.

In order to avoid false triggers of a phase jump compensation scheme in cases of synchronization occurrence, a synchronization detector is provided in the proposed device.

from the first comparison block 28, the shift register 32 and the third element AND 33.

The amplitude of the signals is compared in the first comparison unit 28 with the threshold P, and the comparison result is written into the corresponding cell of the shift register 32. The outputs of the shift register 32 are combined through the third element 33. In the case where in all the UPC channels the phase adjustment is completed , the amplitudes of the siniq, 1, n signals will become less than the threshold and in all cells of the perHctpa shift 32

five

Log.1 will be recorded, the third element AND 33 forms the signal U, allowing compensation of the phase jump Signal and 5 serves to clear the shift register 32 during the initial synchronization. The clock signal serves to shift the information in the shift register 32.

Claims (1)

Formula invented and A device for detecting amplitude-phase-modulated signals containing a group correlator whose outputs are connected to one input of the first block of signal projection, the outputs of which are connected to the inputs of the code converter, the outputs of which are connected to one input 1 of the phase offset analyzer, the other inputs are connected with the outputs of the group correlator, and to the inputs of the decision block, the outputs of which are connected to the inputs of the decoding unit, while the outputs of the phase offset analyzer are connected to sig the primary inputs of the first and second switches, the outputs of which are connected respectively to the first inputs of the first and second adders, the outputs of which are connected respectively to the BbEvi switches to the inputs of the first and second operational memory blocks, the second inputs of which are combined, in order to improve noise immunity during phase jumps, three elements AND, third, fourth, fifth and sixth switches, element 1-SHI, third and fourth adders, two multipliers, two averager, two comparison units, trigger, regis are introduced p shift, the second block of the signal projection recalculation and the amplitude selector, the outputs of which are connected to the control inputs of the first and second switches, with the inputs of the OR element, the output of which is connected to the first input of the first element And, and with the signal inputs of the third switch, the output which is connected to the first input of the first multiplier, VNII1Sh Order 288/59 Circulation 639 Subscription 11proizv-po.gshgr. pr-e, Uzhgorod, st. Project, 4 15 25 922026 the second input of which is connected to the output of the third adder, and to the first input of the second multiplier, the second input of which is connected to the output 5 of the fourth adder, the inputs of which are connected to the inputs of the third adder and with the outputs of the fourth switch, the signal and control inputs of which are connected respectively to one of the analyzer inputs. phase detuning, the other inputs of which are connected to the inputs of the amplitude selector, and the output of the first element And, the second input of which is connected to the output of the trigger, to the input of which is connected the output of the second element And, to the control input of the fifth switch, the output of which is connected to the second input of the first adder, and with the control input of the sixth switch, the output of which is connected to the second input of the second adder, with the outputs of the first and second multipliers through the first and second connectors respectively us to one input of the second signal conversion unit projections other input: of which are connected respectively with the first 30 signal inputs of the fifth and sixth switches, the outputs of which are connected to other inputs of the first block of signal projection recalculation, and with the outputs of the first and second operational storage blocks, outputs, turns of the second block of signal recalculation: tions are connected to the second the signal inputs of the fifth and sixth switches, the output of the second multiplier 40 through the first comparison unit, the second input of which is the first threshold input of the device, is connected to the input of the shift register; the outputs of which are connected to the inputs of the third 45 And that, the output of which is connected to the first input of the second elements and that the second input of which is connected with the output of the second comparator block, k. the first input of which is connected to the output of the second averager, and the second input of the second comparison unit is the second threshold input of the device.