SU1288906A1 - Counting device - Google Patents

Abstract

The invention relates to a pulse technique and can be used as part of digital measuring devices. The purpose of the invention is to increase the speed by allowing the counting of the number of pulses that follow with a frequency higher than the cut-off frequency of the counters. The device contains a distributor 1, a counter 4. To achieve the set goal, an adder 5, an indication unit 6, 2 or more are entered into the device. (L TGTT7T ... PTG 1 gtt

Description

. The invention relates to a pulse technique and can be used as part of digital measuring devices.

The aim of the invention is to extend the frequency range by making it possible to count the number of pulses that follow with a frequency higher than the cut-off frequency of the counters.

FIG. I presents the functional diagram of the counting device; in fig. 2 - time diagrams that show his work.

The counting device contains a valve 1, the input 2 of which is the input of the device, each of the outputs 3 of which are connected to the counting input of the corresponding counter 4, the adder 5 and the display unit 6, the inputs of which are connected to the outputs of the adder, groups of inputs of the same weight connected to the outputs the same weight counters.

The distributor contains the first 7 and second 8 pulse shapers, K elements AND 9, K-1 of key elements 10, 2 (K-1) of serially connected delay elements 11, the input of the first of which is the input of the distributor, and the outputs of each last delay element are connected to the first input of the corresponding key element 10, the output of each of which is connected to a common gate. The first input and the output of each even delay element are connected to the first input of the corresponding element AND 9, the outputs of which are the corresponding outputs 3 of the distributor. The output of the last delay element through the first driver 7 pulses connected to the second inputs of the elements And 9 and to the input of the second driver of the 8 pulses, the output of which is connected to the control input of the key elements 10,

The device works as follows.

Each of the delay elements 11 delays the signal by time C, L,. The first pulse shaper 7 generates square pulse tied to the edges of the input signals, with the output pulse ty being chosen from the ratio t ,. t

U7

 J where t (

input pulse duration. Second

pulse shaper 8 generates rectangular pulses associated with the front to the decay of input signals, and the duration of the output pulses

ty is chosen from the same ratios as the duration of the Key elements 10 by the first input connected to the output of the Corresponding odd delay element 11, and the output connected to the common bus, therefore, when the key elements 10 open the control with a signal from the output of the second driver 8 pulses they shunt the outputs of the odd lag elements, i.e. with the key elements 10 open, signals from the output of odd delay elements to the input of even delay elements do not pass. Duration of the delay b. each delay element must be equal to half the repetition period T of the input pulse sequence o

Adder 5 performs the summation and is the adder of counter codes 4 and produces at its outputs a code of the total number of pulses counted by all the counters at each given moment in time

The operation of the device is explained by timing diagrams (Fig. 2), where a is the sequence of input pulses at the device input; b, c, d, d - pulses at the output, respectively, of the first 11.1, second 11.2, third 11оЗ and fourth 11.4 delay elements; e is the pulse at the input of the penultimate delay element; g, 3 — pulses at the output of the penultimate and last delay elements, respectively; and, to - the location of the pulses at the outputs of the first and second forms, respectively

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worldly figures.

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55

In the initial state, the key elements 10 are turned off by the absence of a control voltage at the output of the second shaper 8 pulses and do not shunt the outputs of odd delay elements, the counters 4 are zeroed (the circuit for setting the counters to the initial state is not shown in Fig. 1), the display unit 6 indicates zero the amount of counter codes 4,

When a counted pulse sequence arrives on the delay line (Fig. 2a), the device starts to operate in the counting mode. Through

the interval t ,, after the occurrence of each pulse at the input of the device, it is observed at the output of the delay element 11.1 (Fig. 26), even after G - at the output of the delay element 11.2 (Fig. 2c), etc. (Fig. 2d, d). At the time of the appearance of the K-2-nd input pulse at the input of the device, the first pulse is detected at the input of the 11.2K-3 delay element (Fig. 2e). After a time interval of 6, the first impulse is reached at the input of the delay element 11.2 F-2 (Fig „2g), and again through, the first impulse appears at the output of the delay element 11.2K-2 (Fig. 2h), while at the input of the device this time there will be a K-th pulse (Fig. 2a), and at the outputs of all even delay elements all counting pulses received from the beginning of operation will be present (Fig. 2c, e).

The pulse from the output of the delay line is fed to the input of the first pulse shaper 7, the output of which (Fig. 2, i) (Normalized is a pulse of length t fed to the second inputs of the AND 9 elements and to the second driver of the pulse 8. Under the influence of this pulse, the elements And 9 are opened, and the pulses from the outputs of all even delay elements, as well as the pulses from the input of the device, each arrive at the input of its counter .4.

Each counter records the states +1, and the adder 5 generates for the display unit a code corresponding to the number K. With a decay, the signal from the output of the first driver 7 pulses starts the second driver 8 pulses, which produces a pulse with duration tу "(figure 2, k), arriving at the control inputs of the key elements 10 and opening these key elements. The discovery of key elements coincides with the appearance of pulses at their inputs (Fig. 2b, g, g) and since the open key elements connect the outputs of odd delay elements with a common bus, these signals do not come to the inputs of subsequent even-numbered delay elements and from further advances along the delay line are withdrawn.

Thus, by the time the pulse device arrives at the input of the device (Fig. 2a), there are no signals in the delay line, the key elements 10 are open and stopped

By this time, the signal at the output of the second generator of 8 pulses and the entire device, except for counters 4, adder 5 and display unit 6, are in the initial state in which it was before the arrival of the first counting pulse. In the future, the operation of the device is repeated.

Since the signals at the inputs of counters 4 appear K times less often than at the input of the device, a similar device can be used to count the number of periodic signals of a known repetition period following a frequency K times exceeding the trigger frequency of the counters 4, which will significantly improve the accuracy of many digital measuring instruments, whose operation is based on counting the number of pulses with a constant repetition period.

Claims (1)

Invention Formula A counting device containing a distributor, the input of which is the input of the counting device, and each of the outputs of which are connected  the counter input of the corresponding counter, characterized in that, in order to expand the frequency range of the input pulses by providing counting pulses with a frequency higher than the threshold frequency of response of the counters, an adder and a display unit, whose inputs are connected to the outputs of the adder, are entered into the same input groups whose weights are connected to the outputs of the same weight counters. moreover, the distributor contains the first and second pulse formers To the elements And, K-1 of the key elements, 2 (Kl) of serially connected delay elements, the input of the first of which is the input of the distributor, the output of each odd delay element is connected to the first input of the corresponding key element, the output each of which is connected to a common bus, the input of the first and the output of each even delay element are connected to the first input of the corresponding element AND whose outputs are the corresponding outputs aspredelitel, the last delay element output via 512889066 the first pulse shaper of the subtours, the output of which is connected to the plug to the second inputs of the AND elements and the equal inputs of the key elements to the input of the second pulse shaper. Compiled by P, Smirnov Editor A. Petrov Tehred L, Serdyukova Proofreader L. Pilipenko 7823/58 Circulation 922 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, d «4/5 Production and printing company, Uzhgorod, st. Project, 4 FIG. 2