SU1284006A1 - Television colour synthesizer - Google Patents

Abstract

The invention provides improved accuracy of color signal generation. The TV color synthesizer contains a synchronous generator 1, a grid generator 2, dividers 3, 4 frequencies (DCH), counters 5, 6, adders 7, 8, 9, inverters 10, 11, 12, digital-to-analog converters (DAC) 13-18, unit 19 is comparable to, voltage source 20, television indicator 21, delay unit 22, multivibrator waiting 23, OR element 24, registers 25-31, control panel 32, memory 33, 34. The grid generator 2 is a discrete raster generator consisting of W, N elements. Using puit 32 controls, registers 28-31 and adders 8, 9 set the coordinates X, y, limiting; area of interest chromaticity diagram. Area codes are sent to addresses from 9

Description

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the inputs of the BP 33, 34. They store the code of control signals, which are changed kosf. division of DCH 3, A. With DCH 3, 4 pulses arrive at acc. counters 5, 6, which are counting the codes of coordinates x, y. In accordance with these codes, the TsDL 13-15 form the color signals of the highlighted area.

chromaticity diagrams. With the help of a point marker, formed with the aid of the e-head unit 22 and the waiting multivibrator 23, an indication is made on the chromaticity diagram. Codes color coordinates of the colors recorded in the registers 25-27, received through the DAC 16-18 on the television indicator 21. 6 np.

one

The invention relates to a television technique and can be used as a generator of color signals.

The purpose of the invention is to improve the accuracy of the formation of color signals.

FIG. 1 shows a structural electrical circuit of a television color synthesizer; in fig. 2 - grid generator; in fig. 3- delay unit; in fig. 4 - remote control; in fig. 5 is a view of an image formed on the screen of a television indicator; in fig. 6 - timing diagrams showing the operation of television color synthesizer

The television color synthesizer contains a synchronizing generator 1, a coordinate grid generator 2, the first 3 and second 4 frequency dividers, the first 5 and second 6 counters, the first 7, the second 8 and the third 9 adders, the first 10, the second 11 and the third 12 inverters, the first 13, the second 14, third 15, fourth 16, fifth 17 and sixth 18 D / A, comparison unit 19, reference voltage source 20, television indicator 21, delay unit 22, standby multivibrator 23, OR element 24, first 25 to second 26 registers, third 27, fourth 28, fifth 29 registers, test 30 and seventh 31 registers, remote control 32, the first 33 and second 34 memory blocks.

The coordinate grid generator 2 (FIG. 2) contains the first 35 and second 36 delay blocks, the first 37 and second 38 triggers, the pulse generator 39, the first counter 40, And 41, the second counter 42.

The delay unit 22 (FIG. 3) contains the first 43 and second 44 pending multivibrators.

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The control panel 32 (Fig. 4) contains a constant voltage source 45, a block 46 and a size setting key block 47, a scale switch 48,

Television color synthesizer works as follows.

The sync generator 1 generates lower and vertical sync pulses on the first and second outputs, respectively, necessary for synchronous operation of all units and nodes of the device; on the third output, a mixture of horizontal and vertical sync pulses for synchronization of the television indicator 21; and on the fourth output, a mixture of horizontal and vertical dying pulses. necessary to form a video signal. Lowercase and frame sync pulses arrive at the inputs of the first 35 and second 36 delay blocks and are delayed by the time required to set the chroma diagrams in an arbitrary place on the screen of the body of the indicator indicator 21. The delayed horizontal and frame sync pulses are fed to the inputs of the first 37 and second 38 flip-flops and set the level 1 on their direct outputs. The signal from the output of the first flip-flop 37 is applied to the synchronization of the input of the pulse generator 39 and starts it. Let f d be the frequency of the generated pulses. These pulses are fed to the input of a left counter 40, which counts N pulses and overflows. The overflow pulse is applied to the R input of the first trigger 37 and resets it to its initial state. The horizontal sync pulses are fed to the input of the zero setting of the first counter 40 in order to establish it before the start of the countdown in the initial state. Similarly level

 from the output of the second trigger 38, it enters the second input of the And 41 element, as a result of which the horizontal sync pulses passed to its first input pass through it. Denote the frequency of the horizontal sync pulses by fee and After counting the N ' horizontal sync signals and my second counter 42 overflows, and the overflow pulse resets the second trigger 38 to its initial state. FIG. 6 and S are lowercase and frame sync pulses; FIG. 6 6 and d - the signals at the outputs of the pulse generator 39 and the element And 41; in fig. 6 3 and e are the signals generated at the outputs of the first 37 and second 38 triggers of the coordinate grid generator 2. Thus, the grid generator 2 is a kind of discrete raster generator consisting of N «N elements. At the first and second outputs, discretization pulses are formed, and at the third and fourth, signals defining the boundaries of the coordinate grid.

At the start of operation of the device, the keys of the blocks 46 and 47 and the switch 48 of the control panel 32 are set to the zero position. In this case, the O level is set at all outputs of the control panel 32. As a result, a zero code is set at the outputs of the first 33 and second 34 memory blocks. With this code, the division inputs K and K, respectively, are set on the control inputs of the first 3 and second 4 frequency dividers. From the output of the first frequency divider 3 to the counting input of the first counter 5, pulses with a frequency fd / K are sent, and to the counting input of the second counter 6 from the output of the second frequency divider 4 - pulses with a frequency ctM P, the pulses to the clock inputs of the first 5 and second 6 counters from the third and fourth outputs of the grid generator 2 from the positive front of the synchronizing pulses, the code zero is set in them, after which they start counting successively the pulses coming respectively from the first 3 outputs: and 4 orogo frequency dividers. The capacitance of the counters is selected from the condition N;, N |, K-N,. Let N. Thus, at the outputs of the first 5

and the second 6 counters, a linearly increasing binary code is generated, which is fed to the information inputs of the first 13 and third 15 digital-to-analog converters. A linearly increasing analog signal is generated at the outputs with an amplitude determined by the magnitude of the reference voltage.

0 Chap supplied to them from the output of the source voltage. At the output of the first digital-to-analog converter 13, a voltage linearly increases along the line, and

the output of the third digital-to-analog converter 15 is a voltage linearly increasing across the field. Linear i increasing binary codes are fed to the input of the first adder 7. The inverted signal from the output of the first inverter 10 is fed to the information input of the second digital-analog converter 14. Pa its output is formed linearly falling signal, which decreases both in the line and in the field (Fig. 5. Thus, the following voltages are formed at the outputs of the first 13, second 14 and third 15 digital-analogue converters eni:

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N - capacity counters. When K (il, the pulses arriving at the inputs of the first and second 4 frequency dividers are not divided by frequency, the chromaticity diagram is completely Q aligned with the coordinate grid. From the output of the first inverter 10, the parallel code goes to the first input of the unit compared 19 which code is set to zero (all bits of the second input are connected to a common spike.) Comparison unit 19 allows recording the moments when the code at the output of the first adder 7 exceeds the maximum code, form5

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Miremush at the outputs of the first 5 and second 6 counters If Q YY Q - those

If the codes are at the outputs of the first 5 and second 6 counters, and Q is the code determined by the capacity of the counters, the signals at the output of the comparison unit 19 are formed, provided

f (t) 0 for QX + Q y.dnlly Q-Qx-Qv xO, f (t) 0 for Qx4-Qy Q OTH Q-Qx-Q ,. As soon as the output of the comparison block 19 through Wits level 1, it goes through the OR 24 element to the gate inputs of the first 13, second 14 and third 15 digital-to-analog converters and prohibits the conversion of the binary code to an analog signal. the second 14 and third 15 digital-to-analog converters of the signal amplitudes are zero. These signals are supplied to the signal inputs of the television indicator 21 and reproduced. The view of the image formed on its screen is shown in FIG. . Using the keys of the control unit 46, the control panel 32 sets the required values of the coordinates X and y, which limit the region of the chromaticity diagram of interest. Using the keys of the block 47, write the code values to the corresponding fourth 28, fifth 29, sixth 30 and seventh 31 registers. Writing codes into registers is carried out from the front (positive) edge of the synchronization pulses generated when the corresponding keys of block 47 are closed. In the fourth register 28

the code x is written, the fifth register is 29, the code is y, the sixth register 30 is code X, and the seventh register 31 is code y,. The output of the switch 48 is set to level 1. At the output of the second B and third 9 adders, codes of the coordinate difference XJ-XQ and Y are generated, VO which are fed to the address inputs of the first 33 and second 34 memory blocks, in the latter in accordance with the difference X - x and y-y recorded codes of control signals supplied to the control inputs of the first 3 and second 4 frequency dividers in accordance with the condition

K, / (xx,); K. y, / (y-yj, This condition provides an increase in the scale by as many times as the area of the selected zone of the chromaticity diagram x ,, - Xc and y, -y less, the dynamic range Xp, yx, 1.l

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0), and the imposition of the selected zone of the chromaticity diagram on the coordinate grid (Fig.ZE). Codes of control signals from the outputs of the first 33 and second 3.4 memory blocks are fed to the control inputs of the first 3 and second 4 frequency dividers. The frequency of the pulses applied to the counting inputs: the first 5 and second 6 counters are determined by the condition

ji l, “and,. They begin to count the pulses arriving at their counting inputs, starting with the x and y coordinate code and the x и and y coordinate code,. In accordance with these codes, the output signals of the first 13, second 4 and third 15 digital-to-analog converters form the color signals of the selected section of the diagram: chromaticity.

With the help of a dot marker formed with the help of a delay unit 22 and a standby multivibrator 23, an indication is given on the chromaticity diagram or of its increased Part of the color of interest. The delay unit 22 provides the job coordinates of the marker X | and y. By delaying the frame sync pulse with the help of the first standby multivibrator 43 of the delay unit 22, the coordinate y is set by time, (Fig.) The positive polarity pulse from the output of the first standby one-shot 43 block is fed to the strobe input of the second standby multivibrator 44. A positive polarity pulse is formed delayed relative to lowercase blue

pulse at time y (Fig. 6). Thus, the pulse at the output of the delay block 22 is delayed relative to the horizontal sync pulses by time, and relative to the frame sync pulses - by the time ty. The pulse at the output of the delay block 22 determines the location of the marker. With the help of the standby multivibrator 23, the required pulse duration is set, which determines the dimensions of the marker in and. The impulse from the output of the standby multivibrator 23 is fed to the second input of the OR element 24, then to the gate inputs of the first 1.3, second 14 and third 5 digital-to-analog converters with the purpose of indicating the marker in the color diagram as a black dot. Simultaneously HMnyjTbc from the output of the waiting multi

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The tuner 23 is applied to the clock inputs of the first 25, second 26, and third 27 registers. From the positive front of this pulse, the codes of the color coordinates of the information inputs from the outputs of the first 5 and second 6 counters and the first 1 O color inverter, which is indicated on the extended portion of the chromaticity diagram using a marker, are recorded in them. These codes are fed to the information inputs of the fourth 16, fifth 17 and sixth 18 digital-analog converters and converted into analog signals. In order to reproduce them on television indicator 21, extinguishing pulses are mixed in by gating the fourth 16, fifth 17 and sixth 18 digital-to-analog converters by pulses from the fourth output of the synchro-generator 1. Thus, at their outputs

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the chromaticity diagram of it marker.

indicated by the point formula of the invention

A television color synthesizer containing a synchronizer, a first and a second inverter, a comparison unit, a first adder, a reference voltage source, a television indicator and a delay unit, characterized in that, in order to improve the accuracy of generating a given color signal, a grid generator is introduced into it the first output of which is connected to the first input of the first counter through the first frequency divider, and the second output through the second frequency divider connected to the first input of the second counter, the output of which is connected to The first input of the first adder, the second input of which is connected to the output of the first counter, and the output connected to the input of the first inverter, the first digital-to-analog converter, the first input of which is connected to the output of the first counting device, and the output connected to the first input of the television indicator, the second digital-to-analog converter, the first input of which is connected to the output of the first inverter, and the output is connected to the second input of the TV / o

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indicator, the third digital-to-analog converter, the first input of which is connected to the output of the second, and the output is connected to the third input of the television indicator, serially connected to the first register, the first input of which is coejyi- with the output of the first counter: 1kA, fourth fourth digital-analogue converter, serially connected the second register, the first input of which is connected to the output of the first inverter, and the fifth digital-to-analog converter connected in series to the third register, the first input of which is connected output of the second counter, and a sixth analog converter, a monostable multivibrator whose input is connected to the output of the delay unit, first and second inputs connected respectively to the first and second clock outputs, an OR gate, the first of which is connected to the output of

comparison, the second input is connected to the output of the standby multivibrator, and the output is connected to the second and the first, second and third analogue converters, the third inputs of which are combined and connected to the output of the reference voltage source, the control panel, a quarter register connected between the first input of the control panel and a second inverter input, a second adder connected in series and a first memory block, the output of which is connected to another input of a first frequency divider, serially connected fifth register, first The input of which is connected to the second output of the control panel, the third inverter, the third adder and the second memory block, the output of which is connected to the second input of the second frequency divider, the sixth register, the first input of which is connected to the third output of the control panel, and the output is connected to the other input of the second adder, as well as the seventh register, the first input of which is connected to the fourth output of the control panel, and the output connected to the other input of the third adder, while the third output of the clock generator is connected to the fourth input of the TV onnogo indicator fourth clock output connected to the combined second inputs of the fourth,

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The fifth and sixth digital-to-analog converters, the third inputs of which are combined and connected to the output of the reference voltage source, a third of the output of the grid generator is connected to the second input of the first counter, the third input of which is connected to the output of the fourth register, the fourth output of the grid generator is connected to the second input the second counter, the third input of which is connected to the output of the fifth register, the output of the waiting multivibrato figure.

pa is connected to the combined second inputs of the first, second and third registers; the fifth control output is connected to the combined second inputs of the fourth, fifth, sixth and seventh registers; the sixth output of the control panel is connected to the combined second inputs of the first and second memory blocks; and the second outputs of the synchronous generator are connected respectively with nepraiM and the second inputs of the grid generator.

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Claims (1)

The claims of the invention ^ A television color synthesizer comprising a synchronizer, first and second inverters, a comparison unit, a first adder, a reference voltage source, a television indicator ^ 5 and a delay unit, characterized in that, in order to increase the accuracy of generating a given color signal, a coordinate generator is introduced into it grid, the first output of which through the first frequency divider is connected to the first input of the first counter, and the second output through the second frequency divider is connected to the first input of the second counter, the output of which is connected to the input of the first adder, the second input of which is connected to the output of the first counter, and the output is connected to the input of the first inverter, the first digital-to-analog converter, the first input of which is connected to the output of the first counter, and the output is connected to the first input of the television indicator, second digital-to-analog converter, first input which is connected to the output of the first inverter, and the output is connected to the second input of the television indicator, the third digital-to-analog converter, the first input of which is connected to the output of the second meter, and the output is connected to the third input of the television indicator, the first register is connected in series, the first input of which is connected to the output of the first counter, and the fourth digital-to-analog converter, the second register in series, the first input of which is connected to the output of the first inverter, and the fifth digital-to-analog converter, in series connected - the third register, the first input of which is connected to the output of the second counter, and the sixth digital-to-analog converter, waiting for the multivibrator, input to which is connected to the output of the delay unit, the first and second inputs of which are connected respectively to the first and second outputs of the clock generator, an OR element, the first one of which is connected to the output of the comparison unit, the second input is connected to the output of the standby multivibrator, and the output is connected to the second inputs of the first , the second and third digital-to-analog converters, the third inputs of which are combined and connected to the output of the reference voltage source, the control panel, the fourth register included between the first input of the control panel and by the course of the second inverter, the second adder and the first memory unit connected in series, the output of which is connected to another input of the first frequency divider, the fifth register is connected in series, the first input of which is connected to the second output of the control panel, the third inverter, the third adder and the second memory unit, the output of which connected to the second input of the second frequency divider, the sixth register, the first input of which is connected to the third output of the control panel, and the output is connected to another input of the second adder, as well as the seventh reg p, the first input of which is connected to the fourth output of the control panel, and an output coupled to another input of the third adder, wherein the third output clock is coupled to a fourth input of the television display, the fourth output timing generator connected to the combined second inputs of the fourth ιό, ⁹ of the fifth and sixth analog converters the third inputs of which are combined and connected to the output of the reference voltage source, the third output of the grid generator 5 is connected to the second input of the first counter, tert the first input of which is connected to the output of the fourth register, the fourth output of the grid generator is connected to the second input of the second counter, the third input of which is connected to the output of the fifth register, the output of the standby multivibrator is connected to the combined second inputs of the first, second and third registers, the fifth the control output is connected to the combined second inputs of the fourth, fifth, sixth and seventh registers, the sixth output of the control panel is connected to the combined second inputs of the first and second memory blocks, and the first the second and second outputs of the clock are connected respectively to the first and second inputs of the grid generator. (ri.2.2 FIG. 5 a ~ And ------------------ 1! „And-; ί I; I1IIIIIIIII1I1IJ1 .. IIIIII1HIIIIL g II IIIIIIIIIIIIIIIIIIIIIHIIIIIII1I ;, || G; ¹ 'ιГтt ο ι Г ^ ~ I || --I ι ι ιе е III Ί G. *; Lru ^1; .......--4 U --- ——1 t [1 ’T Riga 6