SU1280698A1 - Shaft turn angle-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computing and can be used to connect analog information sources with a digital computing device. In order to increase the accuracy, speed and expansion of functional capabilities in the converter of the angle of rotation of the shaft into a code containing a variable voltage driver 1, sine-cosine. rotary transformer 2 (SCRT), one-shot block 3, sequential approximation register 4 (RPP), first 10 and second II memory blocks, first 13 and second 14 digital-to-analog converters (DAC), first comparator 15, the first 6 and second 7 rectifiers are introduced Miteli, shaper 5 code octants, switch 12, second comparator 1b, block 9 elements EXCLUSIVE RSHI, first 17, second 18 and third 19 registers. Rectangular signals from the output of an AC voltage driver I are fed to the primary winding of the SFC. The output voltages of the SCRT are brought into the first quadrant by two full-wave rectifiers 6, 7, the output voltages of which are multiplied by two DACs 13, 14 with the sine and cosine modulus codes obtained by distributing the octant functions recorded in two memory 10, II at an angle, is given (L in the first quadrant. The difference between the output voltages of two PAs is reduced to zero in DFG 4, which is triggered at each half-cycle of the power supply voltage of the SSCT. The DGP output code using the SUSH element block) being young This digit is the octant code, the IND is converted to the ACS angle code within the first 00 octant. The sine and cosine signs are detected on the comparators, and the octant code is generated from the signs and the ratio of the sine and cosine modules. 00 3 h.p. f-ly, 3 ill.

Description

The invention relates to automation and computing and can be used to connect analog information sources with a digital computing device.

The purpose of the invention is to improve the accuracy, speed and expansion of the functionality of the converter angle of rotation of the shaft in the code.

FIG. 1 shows the structural scheme of the proposed converter; in fig. 2 - block diagram of the shaper code octants; in fig. 3 temporary diagram of the converter.

The rotation angle converter. The shaft contains a variable voltage shaper 1, a sine-cosine rotating transformer (CCWT) 2, a one-vibrator block 3 J consisting of two series-connected single-oscillators, a sequential approximation register 4, a shaper 5 octant code, the first 6 and the second 7 meters, block 8 inverters, block

9 elements EXCLUSIVE OR, first

10 and the second 11 memory blocks, the switch 12, the first 13 and the second 14 diffracted-analog converters (D / A converters), the first 15 and the second 16 comparators,

first 17, second 18 and third 19 registers.

The alternating voltage driver 1 comprises a pulse generator 20 in series, a frequency divider 21 and a power amplifier 22.

Switch 12 includes an inverter 23, the first 24 and second 25 blocks of elements AND-OR.

The shaper 5 code octants contains the first 26 and second 27 comparators, the first 28, the second 29, the third 30 and the fourth 31 elements EXCLUSIVE OR.

The power amplifier 22 can be connected to two switches using a bridge circuit, in the diagonal of which the primary winding of the SSCT 2 is turned on. The switches are controlled by the output signals of the splitter 2 frequency.

Converter angle of rotation of the shaft in the code works as follows.

The generator 20 produces clock pulses (fig.Za). In the divider 21, rectangular pulses are generated with a ratio of 2 and a voltage frequency

power supply ACS 2, which are amplified by power in the amplifier 22 (Fig. 3B). At the output of SSC 2, rectangular pulses are formed (Fig. 3 Sv) modulated in amplitude as a sine and cosine of the angle 9 of the rotation of the SSC 2 shaft. Rectifiers 6 and 7 perform a full-wave rectification of the output signals of SSC 2 (Fig. W and H, At the same time, the comparators 26 and 27 of the imaging unit 5 produce single signals corresponding to the positive half periods of the output voltages of the ACS 2.

At the outputs of the EXCLUSIVE OR elements 28, 30 and 31, logical signals are formed corresponding to the values of the first, second and third bits of the angle code 0 (octant code), and the value of the first (senior) bit coincides with the sign of the function sin6, and at the output of the element EXCLUSIVE OR 29 a logical signal is generated corresponding to the sign of the cosS function, i.e.

and ,, s ,,

Uj8 Us,

of. and.

 and

U -U e-Ujg

io

The values of logical signals in the O – 2 range with the single and zero output signals of the divider 21 are given in the table.

The output voltages of the rectifiers 6 and 7 are compared at the comparator 16, as a result of which a logical signal is received at its output j for the following value:

and, b 0, if,; U ,, 1, if

if a ;

and b-1

and. b and.

The first one-shot block 3

runs on the signal edge at each half-period of the output voltage of the 21 frequency divider. At the output of block 3 of one-shot, after a time t ,, equal to the rise time of the output voltages of SQPE 2 to a steady-state value, a negative polarity pulse is formed (Fig. 3e).

Register 4 provides the mode

0 bit balances. The digital outputs of register 4 are connected to the inputs of the memory block 11 directly and through the block 8 of inverters to the input of the memory block 10. In blocks of 10

Claims (4)

5 and 11 are recorded, the tabular values of the sin function from O to Y7 / 2 and from / 2 to 1 when the input code changes from zero to maximum (for example, LSI K505REZ 0068-0071). In this case, at the outputs of blocks 10 and 11, the codes co3N and sinN are formed within the first octant. In the first, fourth, fifth, and eighth octants, the output from block 25 passes the code from the output of memory block 11, and to the output of block 24, the code from the output of block 10 and vice versa, in the second, third, sixth and seventh octants to the Output of block 25 passes the code from the output of block 10, and to the output of block 24 - the code from the output of the AND block, that is, W ,,,. SinN, N cosN in the first. 25 fourth, fifth and eighth octants N-J cosN, N sinN in the second, third, sixth and seventh octants. At the outputs, the D / A converters 14 and 13 form analog signals equal to the product of the signals at their digital and analog inputs. At the output of the comparator 13, a signal is generated that is proportional to the difference in the output voltages of the D / A converter 13 and 14. The resulting error reduces to zero by the method of bit balances in register 4, which is triggered at each half-period of the divider 21 signal. when the output signals of SSC 2 remain unchanged in time. Each conversion cycle is composed of m cycles (Fig. ZJ and ZZ). At the end of the last clock cycle, a zero logic level is formed at the cyclic output of register 4 (Fig. 3i). In this case, the N code at the output of the register 4 is connected with the sine and cosine module sinYHsinQl, coslf lcoB91 by the ratio f in the first, fourth, fifth, and eighth octants; N "/ 2- in the second, third, neck-and seventh octants. The expression for 0 can be written as follows: 9 5i / 4 (n-1) + N in odd octant & I / 4 (p-1) + N in even octants; where N is the inverse of the output code of the register 4 defined by the expression N A / 4-N. The code from the output of register 4 is fed to the input of block 9, another input of which controls the third digit of the angle code. At the same time, the output of block 9 in even-numbered octants is passed by the direct code N, and even-numbered octants - by the inverse code N. The angle code from the output of block 9 together with the code of octants represents the angle code in the range O - 2. At the outputs of blocks 25 and 24, the modulus codes of the sine and cosine of the angle SN „5 sin) f lsin9l, N cozy lcosei are formed. Module codes and the signs of the functions sin6 and COS0, as well as the angle code ft, are recorded in registers 19, 18 and 17 on the negative edge of a pulse from the cyclic output of register 4. The functionality of the converter is enhanced by obtaining sine and cosine of angle codes by using similar devices. for example, to form the sweep voltages of the cathode ray tube, which are formed by multiplying the sine and cosine codes with the sawtooth voltage applied to the analog inputs of the multiplying DAC. Since the converter is turned on at each half-period of the change in the supply voltage of the SCRT 2, its speed at the same frequency of the supply voltage is twice as high. By concurrently forming the three most significant bits of the angle code, a reduction in the duration of the conversion cycle is achieved. The static error of the converter is mainly due to the error of the D / A converters 13 and 14 and rectifiers 6 and 7. As the converter excludes the sample-storage blocks, their instrumental errors, which are larger than the errors of the rectifiers, are also excluded. Claim 1. Shaft rotation angle converter into a code containing an alternating voltage driver, the first and second outputs of which are connected to the inputs of a sine-cosine rotary transformer, a single-vibrator unit, its own sequence approximation, the group of outputs of which through an inverter lock is connected to the inputs of the first memory unit the second block of the first, second and second digital-to-analog converters, the outputs of which are connected to the inputs of the first comparator, the output of the first comparator is connected to the information the sequential approximation register, characterized in that, in order to improve the accuracy, speed and functionality of the converter, the first and second rectifiers, the octant code generator, the second comparator j, the block of EXCLUSIVE OR, first, second and third registers are entered into it , the first and second outputs of the sinus-acidic rotating transformer are connected to the inputs of the first and second rectifiers, respectively, and to the first and second inputs of the octant code generator, t The third input is connected to the third output of the alternating voltage driver, the fourth input is connected to the second comparator, and the first, second and third outputs are connected to the inputs of the higher bits of the first register, the outputs of the first and second rectifiers are connected to the analog inputs of the first and second digital-analog outputs converters, respectively, and to the inputs of the second comparator, the output of which is connected to the control input of the switch, the first and second groups of information inputs of the switch are connected respectively to you With the first and second memory blocks, the first group of inputs of the switch is connected to the digital inputs of the first digital-to-analog converter and to the group of inputs of the second register, the second group of outputs of the switch is connected to the digital inputs of the second digital-analog converter and the group of inputs of the third register is connected to the inputs of the second memory block and to the information inputs of the block of elements EXCLUSIVE OR, the outputs of which are connected to the inputs of the lower bits of the first the first register, the first, third and fourth outputs of the shaper of the octant code are connected respectively to the sign bit of the third register, to the control input of the block of the EXCLUSIVE OR elements and to the sign bit of the second register, the third output of the shaper of the alternating voltage is connected to the input of the one-shot vibrator; which and the fourth output of the alternating voltage driver are connected respectively to the installation and clock inputs of the serial approximation register, the output of which is connected to the synchronization to the relevant inputs of the first, second and third registers, 2, the converter according to claim 1, wherein the variable voltage driver comprises a series-connected pulse generator, a frequency divider and a power amplifier, the outputs of which are the first and second outputs of the variable-voltage driver 5 voltage, the third and fourth outputs of which are respectively the outputs of the frequency divider and the pulse generator, 3, The converter according to claim 1, 1, wherein the switch comprises an inverter, the first and second blocks of AND-OR elements, each of which contains first and second control inputs and the first and second  groups of information inputs, the input of the inverter is the control input of the switch and connected to the first control inputs of the first and second block of AND-OR elements, and the output of the inverter is connected to the second control inputs of the first and second block of AND-OR elements, the first group of information inputs The second block of the AND-OR elements is connected to the second 5 group of information inputs of the first block of the AND-OR element and is the first group of information inputs of the switch, the first group of information inputs of the first block of IL-IL elements And is connected to the second group of information inputs of the second block of AND-OR elements and is the second group of information inputs of the switch, and the outputs of the first and second 45 blocks of the AND-OR elements are respectively the first and second group of outputs of the switch, 1 4. The converter according to claim 1, 20, and 20, which means that the shaper of the octant code contains the first and second comparators, the first, second, third and fourth elements are EXCLUSIVE OR, the first inputs of the primary and second comparators are, respectively, the first and second the inputs of the shaper code octants, the second inputs of the first and second comparators are connected to the common bus. and the outputs of the first and second comparators are connected to one inputs of the first and second elements EXCLUSIVE OR, the other inputs of which are combined and are the third input of the driver, and the outputs are connected to the inputs of the third element EXCLUSIVE OR, the output of which is connected to the single input of the fourth element EXCLUSIVE OR whose other input is the fourth driver input, the outputs of the first, third, fourth, second elements EXCLUSIVE OR are respectively the first, second, third, and fourth outputs of the tors, octants code. GL 5