SU1275418A2 - Device for generating time markers - Google Patents

Abstract

The invention relates to automation and computer technology, in particular to the field of digital data input into a computer using a sample of analog values at regular intervals, and is an improvement of the known device according to the author. No. 885990, The purpose of the invention is to poke the device into a dashboard by reducing the time to generate an error signal during malfunctioning, which is achieved by connecting the first key to the third input of the second key, i Il.

Description

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The invention relates to automation, namely to the field of digital data input into a computer using a sample of analog values at regular intervals, and is an improvement of the known device, according to the author. No. § 85990.

The aim of the invention is to increase the reliability of the device by reducing the time required to generate an error signal during a malfunction,

The drawing shows a block diagram of the device.

The device for generating timestamps contains a pulse generator 1, a frequency divider 2, a three-input first key 3, a first key block A, a memory register 5, a second key block 6, a pulse counter 7, first and second triggers 8 and 9, an OR 10 element, the first, second, third, fourth, and setup inputs J1-15 of the device, the first and second outputs

16 and 17 devices and a three-input second key 18.

The device works in the following way.

In the initial state, the keys 3 and 18 are closed, the trigger 9 is in the initial state, i.e. at the exit

17 device has no signal and the counter 7 is inactive. To start the device, the time interval code is supplied to its installation inputs 15. Then, during the effect of this signal, a pulse is also applied to the device input 14, the key block 4 opens

and the time interval code goes to register 5, where it is stored, and respectively, to the information input of key block 6. At the same time, the pulse from device 4 input through the OR 10 element is fed to the control input of key block 6 and the time interval code is entered into counter 7. a pulse to the device input 12, a steadily opening key 3, and pulses along the circuit: generator 1, divider 2 and key 3 arrive at the counter 7 input. At the same time, the pulse from device input 12 locks key 18 and trips the trigger: 8 to its initial state or confirms this condition. Further, when the counter overflows 7 signal

from its output through the element OR 10 opens the block of 6 keys and again ensures the transfer of the code of the time interval from the register 5 through the block

keys 6 to counter 7, and the cycle repeats. At the same time, the signal from the output of the counter 7 overturns the trigger 8 and at its first output a signal appears, tilting the key 18, and on

the second is a signal that causes the appearance of a time stamp at the output 16 of the device. With the timely response of the computing complex to the time stamp on the input 12 of the device again

a pulse appears, the state of the key 3 is confirmed, the trigger 8 returns to the initial state, the time stamp signal disappears and the key 8 is closed, and so on. In this case, if the computing complex does not respond to the timestamp, the first impulse from the output of the key 3 through the key 18 goes to the trigger 9, overturns it, and the output 17 of the device

An error signal appears, the computing complex starts operating along the emergency branch of the program. At the same time, an impulse is returned to the input 13 of the device, which returns a trigger 9

Into the initial state, and then on the input 12 of the device, an impulse also arrives, causing the operation of the device, similar to the work with timely response of the computing complex.

The termination of the operation of the device is carried out by applying a pulse to the input 11 of the device, the key 3 is stably closed, and the device returns to its original state.

Such an algorithm of the device operation will increase {the reliability of its operation in the computer system, which reduces the loss of the useful time of the latter.

Claims (1)

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