SU1264339A1 - Phase-lock loop - Google Patents

Description

The invention relates to radio engineering and can be used to measure the parameters of short radio pulses.

The purpose of the invention is to increase the speed of the device while maintaining filtering ability.

The drawing shows a structural electrical diagram of a phase-locked loop.

The device for phase-locked loop contains a phase detector 1, a subtractor 2, a voltage-frequency converter 3, a frequency divider 4 with a variable division coefficient (DPKD), a threshold unit 5, a reversible counter 6, a digital-to-analog converter 7, an adder 8, an inertia-free correction link 9, a voltage controlled oscillator 10 and a beat indicator 11.

The device operates as follows.

• When an input signal and a voltage controlled oscillator signal 10 are supplied to the inputs of the phase detector ⁴ , the phase disagreement signal is fed to the input of the subtractor 2 and from the output of the latter to the voltage-frequency converter 3. Assume that the pulse repetition rate of the converter 3 is proportional to the input voltage module, i.e.

^R lnch (. ⁺ ) ^{= To} ANCH / ^and vhpnL ⁺ ) I.

Then the pulse repetition rate from the output DPKD 4

W *) - th ⁴ - K ... (+) 1 ,.

^And DNKA II where N _{A (Tka} ~ division coefficient. DPKD with a variable division coefficient.

In this case, the threshold block 5 determines the sign of U (+) and, in accordance with

I PNC I with this, controls the direction of the pulse counting by the reverse counter 6. With a large digit capacity of the digital-to-analog converter 7 π (. Ί dt N in "pnch; -’

DPKD where U _4an . (+) - voltage at the output of the digital-analogue pre-converter 7;

Ksap “discretization of its output voltage.

Therefore, blocks 3-7 together are a generator with a time constant

T =

Using subtractor 2, the generator is covered by a negative feedback circuit, i.e. it is converted into an inertial link, and due to the inclusion of the inertia-free correction link 9 with the transfer coefficient K, part of the circuit from the input of the subtractor 2 to the output of the adder 8 corresponds to a proportional-integrating filter (phase-delayed link) with the transfer function, K ⁺ ϊ + κ ^rt w ( P) = (HK) -, where P is the differentiation operator.

In the absence of synchronism, the beat indicator 11 provides a logical signal corresponding to the minimum division coefficient N, to the control input of the DPKD 4, while

Mip ify ⁹

-g_k ”to

VLF cash where S _nn

S and <VA

5 _PG band retention of the proposed device; accordingly, the slope of the phase detector 1 and. the slope of the voltage controlled oscillator 10.

Ί

In this case, the parameters are equivalent to a filterless device according to a swotter circuit having a short time of synchronization, i.e., high speed.

After entering synchronism, the beat voltage at the output of the phase detector 1 disappears, the beat indicator 1 1 generates a signal corresponding to the maximum division coefficient N _{MQKC DPKD} 4, the 50-time constant increases by N .. „/ Н _И11 „ times and the proposed device becomes Its parameters are a phase locked loop with a proportionally integrated filter55 and has a small noise band.

Thus, the invention provides improved performance of the proposed device while maintaining filtering ability, i.e.

low noise band in synchronization mode.

Claims (1)

The invention relates to radio engineering and can be used to measure the parameters of short radio pulses. The purpose of the invention is to increase the speed of the device while maintaining the filtering ability. The drawing shows the structures on the electrical circuit of the phase-locked loop device. The phase-locked loop frequency device includes a phase detector 1, a reader 2, a voltage-frequency converter 3, a divider 4 frequencies with a variable division factor (/ SHKD), a threshold unit 5, reversible counter 6, digital-to-analog converter 7, adder 8, inertialess corrective link 9, generator 10 controlled by voltage, and beat indicator 11. The device works as follows. When a phase signal input 1 of the input signal and a voltage controlled oscillator signal 10 are applied to the inputs, the phase mismatch signal is fed to the input of subtractor 2 and from the output of the last to voltage-frequency converter 3, that the pulse frequency of converter 3 is proportional to the input voltage module, t, e. Ul .-) KnH. /U8.n ". (+) /. Then the pulse repetition rate from the output of the PDKD 4 f (4- - HIC-ipm (. +; Ig A U 1 l is the division factor. PDKD 4 with a variable division factor. In this case, the threshold unit 5 determines the sign and (+ ) and in accordance with Vhpmch Vc with this, controls the direction of the pulse counting by a reversing counter 6, If the digital-to-analog converter 7 is large, QvJujCtn „pnch and (+) Un- (t is the voltage at the output of the digital-analog generator 7; - is its output voltage. Consequently, blocks 3–7 are, in combination, a generator with a constant time –j NjfrUK Ifu chpp With the help of a subtractor 2, the generator is captured by a negative feedback circuit, t, e, is converted into an inerion link, and thanks to the inclusion of a zero-free corrective vein 9 with a transfer coefficient K of the circuit from the input of the subtractor 2 to the output of the adder 8 the link with the phase delay) transfer function 1 n; to W (P) (HK) de - differentiation operator, In the absence of synchronism, the indicator of 11 beats causes a logical signal corresponding to the minimum coefficient itsintu dividing N,, wherein s 1 j 1 v .achI where Ry (1 "-K) 5" r, - retention strip of the device; S and. - respectively, the steepness of the phase detector 1 and. the slope of the generator 10, controlled by voltage, In this case, the device is equivalent in its parameters to a filterless circuit with a short time to synchronization, t, e, high speed. After synchronization, the beat voltage at the output of the phase detector I disappears, the beat indicator 1 1 hits the signal corresponding to the maximum division ratio N DCD 4, the time constant increases by N yN, and the proposed device becomes in its parameters the system of phase self-tuning frequency proportional-integrating filter and has a small noise band. Thus, the invention provides an increase in the speed of the proposed device while maintaining -. filtering capacity, i.e. low noise band in sync chronism mode. Claims A phase locked loop device comprising a series connected phase detector, the first input of which is the input of the device, an instantaneous correction link, an adder, to the second input of which a reversible counter is connected via a digital-to-analog converter, and a voltage controlled oscillator whose output is connected to the second input of the phase detector, as well as the threshold unit, the output of which is connected to the ЗЯ4. with a control input of a reversible counter, characterized in that, in order to improve speed while maintaining its filtering ability, between the output of the phase detector and the counting input of the reversible counter are connected a series-connected subtractor, the second input of which is connected to the output of a digital-analogue converter, a voltage converter frequency and divider with variable division factor, between the control input of which and the output of the phase detector the beat indicator is turned on, and the output of the threshold unit connected to the output of the subtractor.