SU1259502A1 - Digital signal regenerator - Google Patents

Abstract

The invention relates to telecommunications technology. The possibility of allocating channel numbers with statistical compaction is ensured. The device contains a correction amplifier 1, two threshold blocks 2 and 3, a block for selecting a timing signal 4, a clock signal receiver 5 and a terminal OR 6. To achieve the goal, a signal separation unit 7, a decoder 8 channel number, channel keys 9 are entered into the device. , priority block 10, adder 11, comparison block 12, channel number formation block 13, signal combiner 14, switch block 15, three delay blocks 16, 17 and 18, information replacement block 19, switch 20, W 21, element control block 22 and linear wave former 23, using a cat ryh kvazitroichnogo from the input signal in the code with a variable alternating current Iol p- NOSTA vschel parcels are digital channels with a random packing. 1 il. (Ls

Description

The invention relates to telecommunications engineering and can be used in digital communication systems for carrying out a regeneration process.

The purpose of the invention is to provide the possibility of separating digital channels with statistical multiplexing.

The drawing shows a structural electrical circuit of the proposed generator.

The digital signal generator contains a correction amplifier 1, the first 2 and second 3 threshold blocks, a timing signal allocation unit 4, a clock signal receiver 5, the first element OR 6, a signal separation unit 7, a decoder 8 channel number channel keys 9, priority units Yu, an adder 11, comparison unit 52, channel number generation unit 13, signal combining unit 14, switching unit 15, first 16, second

17 and the third 18 delay blocks, the information replacement block 19, the switch 20, the second element OR 21, the control block 22, the linear signal generator 23.

The regenerator digital signals works as follows.

A quasi-macro signal in the code with alternating polarity of the current parcels (AMI code) from the forward direction line arrives at the input of the regenerator. This signal corresponds to the signal generated in the channel-forming equipment of digital transmission systems by combining the address of the most active channel and information about its state, followed by conversion to a quasi-terrestrial signal. Signals of positive polarity come from the first output of the amplifier 1, and the second signal - negative signals. The signals regenerated by the first 2 and second 3 threshold blocks are combined by the first element OR 6 and form the initial binary signal, which is fed to the clock receiver 5, the signal separation unit 7 and through the third block

18 delay on the unit 15 switching. The receiver 5 of the sync signal determines the location of information symbols on the status of the channels and the addresses of the channels in the incoming binary sequence, and the separation block 7 separates them and transmits from the first output the information on the status of the channel to the first

The inputs of the channel keys are 9, and from the second - information about its number on the decoder B channel numbers.

To the second inputs of channel keys

9 receives a control command from a channel number decoder 8, which permits the passage of information symbols to one of priority blocks 10 if this channel is not allocated, and gives a command to output information from the channel key if a channel is transmitted via a line ( assign i) to the selected channel, adder 11 combines the signals from the channel priority blocks 10 (excluding the i channel), and sends to the first input of the comparison unit 12, the second input of which receives information through the corresponding block

10 priority about the condition of the i-th channel. Information about the state of the i-ro channel also goes to block 14 of the signal combiner, where the unification of the state information occurs.

channel and its number, formed in block 13 of the formation of the channel number. Comparison unit 12 determines (taking into account priority) which of the channels is the most active: input

or transmitted over the communication line, and gives a command to the switching unit 15; . for the passage of information about the state of the most active channel. Information about the most active

channel enters the third input unit 19 replacement information.

 The first and second inputs of the information replacement unit 19 through the first 16 and second 17 delay units receive signals about the positive and negative polarity packages being regenerated. In information replacement block 19, information in the forward direction line is replaced with a signal from the switching unit 15. If the signal after the information replacement block 19 is directly converted into a quasitrotic, i.e., the positive polarity is assigned to the current signals of the first output of the information replacement block 19, and the negative polarity is given to the current signals of the second output, then in the regulating quasitroic signal as a dyuh successive one polarity. Transmission of such a signal is not allowed.

3

To avoid this, the switch 20, the control unit 22 and the second element OR 21, the Control unit .22 of the control are transferred from one state to another if the character of the input signal (coming from the switching unit 15) and the signal to be replaced (coming from the second element OR 21) on the input does not match. In switch 20, signals are transmitted from the first input to the first output and from the second input to the second output in the absence of a command from the control unit 22 and the first input to the second output and the second input to the first output are transmitted if such a command arrives. Due to this, preservation of the transformation law is achieved and the signal from the output of the linear signal generator 23 is fed to the consumer of information

Claims (1)

Invention Formula A digital signal regenerator containing a correction amplifier, the outputs of which are connected to the inputs of the timing signal extraction unit, the output of which is connected to the first input of the clock signal receiver, and to the first inputs of the threshold units, the second inputs and outputs of which are connected respectively to the output of the clock signal and with the inputs of the first element OR whose output is connected to the second input clock receiver, as well as information replacement unit, the outputs of which are connected to the information inputs of the switch, the control input and outputs of which are connected respectively to the output of the control unit and to the inputs of the linear signal forwarder A. Moskevich Editor M, Blanar Tehred L. Serdazhova Corrector A. Zimokrsrv 5140/58 Circulation 624 Subscription VNISh USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Design, 4. 59502А In order to enable digital channels with statistical multiplexing, J includes three delay blocks, channel keys, a signal separation unit, a comparison unit, a second OR element, priority blocks, a channel number decoder, an adder and in series 10 connected to a channel number generation unit, a signal combining unit and a switching unit, the output of which is connected to the first input of the control unit, the second input of which is connected to the output of the second OR element, and to the control unit block information replacement, the signal inputs of which are connected to the inputs of the second element OR and the outputs of the first 0 and the second delay unit, the inputs of which are connected to the inputs of the first SHS element, the output of which is connected to the input of the third delay unit, the output of which is connected to the second 5 by the input of the switching unit, and to the first input of the signal separation unit, the second input and the first output of which are connected respectively to the output of the clock signal receiver and to the input 0 of the channel number decoder, the outputs of which are connected to the first inputs of channel switches, the second inputs of which are connected to the second output of the signal separation unit, while the outputs 5 corresponding channel keys through one priority blocks are connected to the inputs of the adder, the output of which is connected to the first input of the comparison unit, the second input and output of which connected respectively to the output of another priority block, whose input is connected to the second one of the signal combiner, and to the third input of the switching unit.