SU1259271A1 - Test generator - Google Patents

Abstract

The invention relates to automation and computing and can be used in the test control of logic blocks. The purpose of the invention is to increase the speed. The operation of the test driver with reference to a device for control of logic blocks is considered. First, the device determines the inputs / outputs of the monitored unit, this information arrives at the address inputs of the test generator. Depending on this code triggers are triggered in. Kazzdom discharges the test driver and test information to the controlled unit. The test driver can operate in a counter mode with a variable number of bits. 4 il.

Description

The invention relates to automation and computing and can be used in the test control of logic blocks.

The purpose of the invention is to increase speed.

Fig. 1 shows a functional diagram of the test driver, Fig 2, an example of the use of the test processor for test control of logic blocks, Fig. 3, a block diagram of the control unit; in fig. 4 is a timing diagram of the operation of the control unit.

The device (Fig. 1) contains the trigger 1 of the installation element AND 2 of the control, the trigger 3 of the start of formation, the elements OR 4 and 5, bits 6.1, ..., 6.p of the discharge test generator contain the triggers 7.1, ..., 7.n, elements And 8.1, ..., 8, p and 9.1 ,. 9.P, elements of RShI 10.1, ..., IQ.n, elements OR 11.5, ..., pp, elements AND 12.1, ..., 12.p, elements AND 13.1 ..., 13.p -1, elements OR 14.1, .. ,, 14.P-1 and elements OR 15.1.0 .., 15.P-1.

FIG. 2 shows: a pulse clock generator 16, a test driver 17, a controlled logic unit 18, a standard storage unit 19, a reference comparison unit 20 consisting of bits 20.1, ..., 20.n.

21 memory consisting of elements 1.

21.1, ... 21.p of memory, display unit 22, blocks 23.1, .... 23. Parameters of inputs-outputs, keys 2A, 1, ..., 24.p, control block 25, switches 26 and 27, driver 28 of control signals and elements And 29.1, ..., 29.p.

The control signal generator (FIG. 3) contains AND elements 30 and 315 pulse drivers 32 and 33, an IL 34 element, a trigger 35, a counter 36, and a decoder 37.

The operation of the test builder is illustrated by the example of its operation in the device for controlling the logical blocks shown in FIG. 2

The device operates according to the principle of comparing the input and output signals of two identical blocks — the controlled block 18 and the block 19 for storing standards; (Fig. 2). The input signals are fed to the comparison circuit 20 from the driver of the 17 tests through the elements AND 29, the input / input determination units 23, and compared with the reaction from the standard-storage unit 19. Comparison of them is necessary for detecting faults in the monitored block 19, such as a short circuit across the inputs. Thus, the output signals arrive at block 20 in comparison with the output pins of the monitored block 18 and block 19

storage standards. Mismatch

the values of the outputs of the monitored block and the storage unit of standards are stored by the memory elements of the memory block 21 and form a fault vector characterizing the location of the faulty element in the monitored block. ke 18,

Switch 26 has two positions: the first, the second corresponds to the control of logic blocks, the second to the control of the microcircuits. In the first mode, the elements AND 29 are opened and the keys 24 are closed, which ensures the transmission of test (input) signals from the driver 17 tests to the inputs of the monitored unit 18 and the unit 19 for storing the standards. In the second mode, the elements And 29 zakryshayut-, but at the same time open the keys 24, which ensures the transmission of input signals from the inputs of the controlled unit 18 (chips) to the inputs of the unit 19 for storing the standards. Initially, all the memory elements 21 and the I / O definition blocks 23, the test driver 17, the triggers 3 and 5, and the counter 36 are set to the zero state, which corresponds to the absence of luminescence

on the display elements-, the display unit 22, closing the keys 24, prohibiting the passage of pulses by the generator of the pulses to the outputs of the test driver I7, and prohibiting the effects of the outputs of the test recorder 17 to the blocks 23 for determining the inputs-outputs and to the outputs of the monitored block 18 and the block 19 standards storage. Trigger 1

installation is set to one.

The device works as follows.

. A switch 27 starts a single impulse generator 32 (and in FIG. 4), which triggers 35 to a single state. A high logic level at the output

the trigger 35 (U., in Fig. 4) permits the passage of pulses from the generator 16 clock pulses to the counters 36 of the driver 28 control signals,

The decoder 37 generates the following control signals (FIG. 4).

When the state of the 36,000 counter is high, a high logic level is produced at its inverse output (U which permits, in case of a single state of the trigger 35, the arrival of pulses from the clock generator 16 to the counter 36. A high logic level at the inverse output of the decoder 37 (T-A) saved to counter state 36 101.

In the state of the counter .36 001, a control pulse (U) is outputted at the output of the decoder 37, which, arriving at the start inputs of the input-output determination units, connects a shunt circuit for fixing the outputs of the storage unit of standards with open collector outputs.

When the counter 36 010 is in state, the control pulse (l. A) is released at the output of the decoder 37 and the trigger is fed to the reset input of the display unit 22, set them to the zero state, and to the zero inputs of the input-output determination units 23. On this control pulse, the input-output determination blocks determine the inputs and outputs from the terminals of the standards storage unit 19. The outputs of the monitored unit 18 and the storage unit 19 of the standards are disconnected from the test driver 17, and the inputs are connected to the corresponding outputs of the test driver 17.

When the counter 36 011 is in state, a control impulse (11) is generated at the output of the decoder 37, which is fed to the locking inputs of the input-output determination units, which disables the shunt locking circuit of the outputs with open collector outputs.

In the state of the counter 36 100 at the output of the decoder 37, the control impulse (U), which is fed to the input of the generator of the test generator 17, is set, sets the triggers 7 of those bits to the zero state, which correspond to

five

U 15

20 25

all right

five

0

pin numbers defined as inputs for the standard storage unit 19 and the monitored block 18. At the same time, trigger 3 is set to 3 (start of control) and trigger one-trigger in one state.

The state of the counter 36 101 at the output of the decoder 37 produces a control potential (U), which enters the input of the OR 15 element and permits the passage of pulses from the generator 16 clock pulses to the synchronization input of the driver 17 of the tests, prohibiting the passage of the same pulses through the AND 30 element the counter input of counter 36. The latter stops, and its state, equal to 101, remains unchanged until the completion of the control of the logic block, i.e. prior to setting the zero state of the trigger 35.

The shaper of 17 tests works in the following way.

After the inputs and outputs have been defined, the input / output determination units at their outputs (inverse outputs of the triggers) appear high or low logic levels. A high logic level at the outputs of the input-output determination units appears when the output is fixed at the corresponding output of the standards storage unit 19. These logic levels arrive at the address inputs of the test driver 17 and, through the corresponding elements OR 10, firmly hold the corresponding triggers in the zero state. At the same time, these Logical Levels open elements AND 8 and 9 to create bypass circuits for both clock pulses and information transfers from bit to bit, mines bits that are defined as output outputs of the monitored unit 18 and unit 19 for storing standards . Low logic levels corresponding to the input terminals of the monitored unit 18 and the standard storage unit 19 do not affect the grade through the elements OR 10 (the reset inputs of the triggers 7 simultaneously close the bypass circuits through the AND 8 elements for the clock pulses and through the AND 9 elements for informational transfers.

51

Since a logic high appears in the test mode input of the test driver 17 (in the state of the counter 3601, U in FIG. 4), the And 2 element is opened by its second and third inputs for passing sync pulses. At the third input element 2 is present: high logic level with inverse trigger output -5 (start control). Elements 12 are closed by a low logic level from the direct output of the same trigger 3. Therefore, in the zero state of trigger 3, the test driver works as a register shift pulse of the setup, since the feedback circuits of the inverted output of trigger switches with their information inputs (V -inputs). in this case, are broken by the closed elements I) 2,

. The shift of the pulse of the installation is as follows.

On admission to sync

The driver of 17 pulse tests from the generator of 16 clock pulses through the open element OR 15 it passes to the counting input of the trigger 7.1 and through the element I 2 to the counting input of the trigger 1 of the installation. Since the information input of the trigger 7.1 after {) without the OR element .11 is set to a high logic level of the direct output of the trigger 1 start, the latter is set to the logical state O with the delay of the pulse passing through the element 2, the trigger 7.1 is set to single state. This happens if at the first bit of the address address of the test driver there is a low logic level corresponding to the definition of this output by the input-output definition unit as the input output of the monitored unit 18 and the unit 19 for storing the standards. The next generator of the 16 clock pulses of the trigger 1 is set to the zero state, since its information input already sets the logic level O from the start trigger 1 output, and the single state of the trigger 1 is transferred to the next trigger 7.1 ..., n, n is the number of inputs and outputs of the controlled block or the length of the test set), which

s 0

five

five

0

has a logical information level at the corresponding information input.

Consider an example of bypassing the pulse of setting the bits of the test driver defined by the input-output definition unit as the outputs of the monitored block 18 and the standard storage unit 19 under the following conditions: the first bit is defined by block 23 as the output terminal, and the second bit is defined as input output logical blocks. In this case, a high logic level from the output of the trigger I of the installation pulse arrives through the open element AND 9.1, the element OR 15.1 to the information input of the trigger 7.2, and the pulse from the generator 16 clock pulses goes to the synchronous input of the trigger 1, through the elements AND 8.1, OR P. .2, and 13.1, or 14.1 - to the synchronous input of the trigger 7.2. This impulse sets the trigger 1 for the start to the zero state, since its information input contains a constant logic level O, and there is no setting impulse at the reset input. In addition, the pulse of the clock generator sets the trigger 7.2 to the single state, since its information input has a single logic level, and the reset input has a logic level O, Trigger 7.1, although its information input also has a high the logic level, is not transferred to the unit state, since at its reset input there is a high logic level, which, arriving from the input-output determination unit through the OR 11.1 element, is firm: it holds the trigger 7.1 in Nya Ullevi state.

The second pulse of the clock generator translates the next allowed trigger 7.1 into the one state and sets the trigger 7.2 to the zero state.

Thus, for the number of pulses equal to K (where K- is the number of outputs of the monitored block 18 and the standard storage unit 19 defined as inputs), the setting pulse passes through all the bits of the test generator corresponding to the input alterations of the monitored unit 18 and the standard storage unit 19. So

as in the remaining bits of the test builder at this moment there is a logical O, the installation pulse, arriving at the installation input of the monitored unit 18 and the standard storage unit 19, sets their internal memory elements to the zero state according to their zero information inputs.

When the K + 1-st pulse of the clock pulses comes in, the trigger 3 is transferred to the active state, since its information input through the OR 5 element is a high logic level, the high logic level from the trigger output 3 goes to the inputs elements 12,1-12. p, thus opening the feedback circuit of the trigger 7.1-7, their inverse outputs with information inputs, which puts the test driver in the binary counter mode with a variable number of bits. In the binary counting process, only those bits of the test builder that are determined by the input-output definition blocks as input pins of the monitored unit 18 and the standard storage unit 19 are involved. ,

Consider an example of operation of the test driver in the counting mode, when its first address bit is defined as the output pin of the monitored block, and the second and nth address bits are defined as the input pin of the monitored block 18 and the standard storage block 19.

In this case, the first address input (FIG. 1) has a high logic level, and on the second and nth address inputs the logic signal O, Trigger 7.1 is firmly held in the zero state, and triggers 7.2 and 7.h have the ability to update their states depending on the states on the information and

synchronous inputs, since at their reset inputs there is a logic level O, therefore the first pulse of the clock generator sets through the elements AND iB.l, OR 11.2, AND 13.1, OR 14.1, trigger 7.2 into one state, since

Through elements 12,2 and ls 15,1- at its information input there is a high logical level of its own inverse output. This first clock pulse

pulses does not change the state of trigger 1, since there is no logical 1 at its input to reset, and it does not pass through the closed element AND 8.2 for subsequent bits of the test driver, the second pulse of the clock generator through the elements AND 8.1, OR 11 , 2, AND 13.1, OR 14.1 sets the trigger to the zero state and, by cutting off its transition from one state to zero, through the elements ,,,, OR 11.П, And 13.П, OR 14 sets it to one state trigger 7.p. - The final binary combination of the test driver is the 111, ... combination, the number of bits of this combination is determined by the number of inputs of the reference and control units, t, e, is K, The next pulse of the vaK generator of pulses sets the test driver to the state 000 .. Oh, therefore a sign of ending

the control of the logic block on all binary combinations of the test driver is the transition of the last trigger 7, and the test driver to the zero state. The cut-off transition of this trigger to the zero state enters the input of the imaging unit 31 — a single pulse (Ug in FIG. 4), Element I 31. is open for passing this positive front only when the counter is 36,101, i.e. when inputs have been defined and the test driver is configured for the corresponding inputs. Therefore transients,

Occurring at the initial stage of the device operation, do not affect the control unit. A single pulse from the output of the imager 33 sets the trigger 35 to zero

the state and thereby the counter 36 is set to the state 000,

The process of controlling a logic block in all test driver combinations is over. The luminescence of the display elements determines the fault vector, which characterizes the type and location of the faulty element of the logic unit. The absence of luminosity of indicators means the operability of the controlled logical block. The memory elements are opened through the third control ™ inputs only after a preliminary passage through all

input pins of the installation pulse, i.e. only after installing the trigger in a single unit. Zum provides presetting of the internal memory elements of the monitored and reference blocks to their original state.

formula of invention

Test driver containing each iM bit (,.,., N, where is the length of the test set vector), rigger, right and second elements AND, | 5 and the direct outputs of the trigger for all bits are information outputs of the test driver, the group of address inputs of which are connected to the first inputs of the first elements AND 20 of all bits, the synchronization input of the test driver is connected to the synchronous input of the first discharge trigger and the second input of the first element I of the first discharge, about 25 and and in order to increase speed, o contains the setup trigger, the trigger of the formation, the AND control, the first and second OR elements, and 30 each bit contains the third AND element, the first and second OR elements, each bit, except the first, also contains the fourth AND element, the third and the fourth element 35 OR, and the single input of the initial setup trigger is connected to the installation input of the test driver, with the first inputs of the first OR elements of all bits and the reset trigger input / start of the formation whose formation is the direct output the sign of the beginning of the formation of the test driver and connected to the first inputs of the second elements I 45. all bits and the first inputs of the third elements AND bits from the second to the n-th, the second inputs of the second elements And all bits are connected to the inverse inputs of the corresponding triggers bits, the outputs of the first elements and all bits, except the first, are connected to the first inputs of the second elements OR bits from the second to the nth, the output of the first element 55 and the n-th digit is connected to the first input of the first element of the scientific research institute, the output of which is output m feature

the end of the formation of tests of the test driver, the inputs of the first elements of the KPI of all bits are connected to the reset inputs of the trigger bits of the same name, the direct outputs of which, with the exception of the output of the n-th trigger, are connected to the second inlets of the second elements OR bits from the second on the nth, respectively, and with the first inputs of the third OR elements, bits from the second to the nth, respectively, the direct output of the nth digit trigger is connected to the second input of the first OR element and the first input of the second OR element, whose output is connected to formatting trigger input of the beginning of the formation, the inverse output of which is connected to the first input of the control AND element, the second input of which is the input of setting the test driver operation modes, the output of the control AND element is connected to the first inputs of the third element OR bits from the second to the fifth, s the trigger synchronization inputs of the start of the formation and the setup trigger, the information input of which is connected to the zero potential bus of the test driver, the first inputs of the fourth elements and bits from the second to the nth socket ina with the corresponding inputs of the address group of the test driver's inputs and the second inputs of the first elements OR of the same-named bits, the second inputs of the fourth elements AND the bits from the second to the n-th are connected to the outputs of the third elements OR of the same-named bits and information inputs of the same-name triggers, the second input of the third element and the first discharge is connected to the direct output of the setup trigger and to the first input of the second element OR the first discharge, the second input of which is connected to the output of the second element AND the first About the bit, the output of the second element IL of the first bit is connected to the information input of the first trigger, the outputs of the third elements AND of all bits, except for the nth, are connected to the second inputs of the third elements OR from the second bit to the nth, respectively , the output of the third element And the n-th bit is connected to the second input of the second element IL1T, the outputs of the first elements OR of all bits are connected to the reset inputs

11 1

triggers of the same name bits, the outputs of the third element OR of all bits, except the first, are connected to the synchronization inputs of the trigger bits from the second to the nth, respectively, and the second inputs of the first elements And the bit dv from the second to the nth, outputs of the second of the OR elements of all bits, with the exception of the first, are connected to the second inputs of the third element AND the bits from the second to

59271, 12

nth, outputs of the fourth elements AND bits from the second to the nth are connected to the second inputs of the third elements OR of the same name bits, the third input 5 of the AND element of the control is connected to the synchronization input of the device, the outputs of the second elements AND bits from the second to n th are connected to the third, three inputs of the third elements OR of the same name bits,

ten

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Compiled by A, Sirotskka Editor N. Yatsola Tehred i.Popovich Corrector G. Reshetnik.

Order 5123/47 Circulation, 671Subscription

VNIIGM USSR State Committee

on affairs of inventions and discoveries 113P35, Oskva, Zh-35, Raushsk nab., d. 4/5

Production and Production Enterprise, Uzhgorod, st. Project, 4

Claims (1)

Claim A test generator containing in each ΐth digit (i = l, ..., n, where η is the length of the test set vector), a trigger, the first and second AND elements, and the direct outputs of the triggers of all bits are information outputs of the test generator, the group of address inputs of which is connected to the first inputs of the first elements AND of all bits, the synchronization input of the test driver is connected to the sync input of the trigger of the first category and the second input of the first element AND of the first category, which differs in that, in order to improve performance he sod The setup trigger, the start trigger, the AND element, the first and second OR elements, and each digit contains the third AND element, the first and second OR elements, each digit, except for the first, also contains the fourth AND element, the third and fourth OR elements moreover, the single input of the trigger of the initial installation is connected to the input of the test driver setup, with the first inputs of the first OR elements of all digits and the reset input of the trigger for the start of formation, the direct output of which is the output of the start the shaper of the test driver and is connected to the first inputs of the second elements AND of all bits and the first inputs of the third elements and bits of the second to the n-th, the second inputs of the second elements and of all bits are connected to the inverse inputs of the triggers of the corresponding bits, the outputs of the first elements AND of all bits, except the first, connected to the first inputs of the second elements OR discharges from the second to the n-th, the output of the first element AND of the η-th category is connected to the first input of the first OR element, the output of which is the output of the end anija test driver test, an output of first OR of all stages are connected to the reset inputs of similar flip-flops 5 digits, the direct outputs of which, with the exception of the output of the η-th trigger trigger, are connected to the second inputs of the second elements OR discharges from the second to the n-th, respectively, and to the first 10 inputs of the third elements OR discharges of the second to the n-th respectively the output of the trigger of the nth category is connected to the second input of the first OR element and the first input 15 of the second OR element, the output of which is connected to the information input of the start trigger, whose inverse output is connected to the first input of the AND element, the second 20 input to This is the input of setting the operating conditions of the test driver, the output of the AND control element is connected to the first inputs of the third elements OR bits from the second to the 25th, with the synchronization inputs of the start trigger and the installation trigger, the information input of which is connected to the zero potential bus of the test driver, per30 outside the inputs of the fourth elements And digits from the second to the n-th are connected to the corresponding inputs of the address group of inputs of the test driver and the second inputs of the first elements OR 35 ° ^Nominal digits, the second inputs of the fourth elements AND digits from the second to the n-th are connected to the outputs of the third elements OR of the same digits and information inputs 40 triggers of the same category, the second input of the third AND element of the first discharge is connected to the direct output of the installation trigger and the first input of the second OR element of the first discharge45 yes, the second input of which is connected to the output of the second AND element of the first discharge, the output of the second OR element. of the first category is connected to the information input of the trigger of the first time of the 50th Series, the outputs of the third AND elements of all discharges, except for the nth, are connected to the second inputs of the third OR elements from the second discharge to the nth, respectively, the output of the third 55th element of the nth discharge is connected with the second input of the second OR element, the outputs of the first OR elements of all bits are connected to the reset inputs 1 1 triggers of the same category, the outputs of the third elements OR of all bits except the first are connected to the synchronization inputs of the triggers of the bits from the second to the fifth, respectively, 5 but also to the second inputs of the first elements and the bits from the second to the fifth, the outputs of the second elements OR of all discharges, with the exception of the first, connected to the second inputs of the third 10 elements And discharges from the second to 1259271. 12 n-th, the outputs of the fourth elements And bits from the second to the fifth are connected to the second inputs of the third elements OR of the same bits, the third input of the control element And is connected to the synchronization input of the device, the outputs of the second elements And bits from the second to p-th are connected to third inputs of the third elements OR of the same category, FIG. 3 gee / L L L P P G p p p p g of □ ..............................— J U * G ^- --—............. < ...... Ί Ur Γ “Ί ΓΊ 1 Ifo ΓΊ ....... Us J ~~ L Us g -1 Ua .......................... Ί ........ :or iu G --- • ΓΊ Fig. H 1 Compiled by A, Orphan Editor N. Yatsola Tehred I.Popovich Proofreader G. Reshetnik Order 5123/47 Circulation, 671 Subscription VNIIIPI of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushskaya embankment, 4/5 Production and printing company, Uzhhorod, st. Project, 4