SU1257836A1 - Majority logic element - Google Patents

Abstract

The device relates to a pulse technique, can be used in the construction of redundant equipment with logic elements. The aim of the invention is to increase the reliability of the operation of the majority element. To achieve this goal, the device containing the initial launch unit 1, the zero reset unit 2, the first 3 and second 4 elements OR, and in each channel the first AND 5 element, the reserved block 6, the second 7 and third 8 AND elements, 9 and 10 restart, delay unit 11, generator 12 clock pulses, element OR 13, AND element NOT 14. Also, element OR 15, blocks 16, 17 are added to each channel. In the description of the invention, functional diagrams of a delay block, a first and a second comparison block, initial and restart blocks, a zero block are presented. The signals at the outputs of the first 16 and second 17 comparison units are used to determine the state of the device. This device does not require additional elements to diagnose failures. 7 il. (Л г-1 Hh ю О1 00 оо О5

Description

The invention relates to a pulse technique and can be used in the construction of redundant equipment with logic elements.

The aim of the invention is to increase the reliability of the operation of the majority element.

FIG. Figure 1 shows the structural electrical circuit of the device proposed; in fig. 2-7, respectively, functional diagrams of the delay unit, the first comparison unit, the second comparison unit, the initial start-up unit, the restart unit and the zeroing unit.

The majority logic element (Fig. 1) contains the initial launch unit 1, the zeroing unit 2, the first 3 and second 4 OR elements and in each channel the first element 5 AND, the first input of which is connected to the information output of the reserved block 6 of the corresponding channel, and the output connected to the corresponding input of the first element OR, the output of which is connected to the output of the device, the output of the second element OR is connected to the inputs of the initial installation of the reserved blocks of all channels. The first and second inputs of the second element OR are connected respectively to the output of the zeroing unit and the first output of the initial start-up unit.

The device also contains the second 7 and third 8 elements And, the first 9 and second 10 restart blocks, the block 11 of the delay, the generator 12 clock pulses, the third element OR 13, the element AND NOT 14 and in each channel the fourth element OR 15, the first 16 and the second 17 comparison blocks.

The setup input of the first comparison unit 16 of each channel is connected to the output of the third element OR 13, the first and second inputs of which are connected respectively to the second output of the initial start-up unit 1 and the output of the first restarting unit 9, the input of which is connected to the zeroing unit 2 input, the first input of the third element AND 8 and the output of the second element AND 7, the inputs of which are connected to the outputs of the first blocks 16 of the comparison and the first input of the fourth element OR 15 of the corresponding channel, the output of the fourth element OR 15 connect not with the first information input of the second comparison block 17 of the same channel, the setup input of which is connected to the output of the second restarting unit 10, the input of which is connected to the output of the delay block 11, the clock and information inputs of which are connected respectively to the output of the 12 clock pulse generator and the output of the third the element AND 8, the second input of which is connected to the output of the element AND-HE 14, the inputs of which are connected to the output of the second comparison unit 17 and the second input of the first element 5 of the corresponding ka

Nala The second information input of each second comparison block of the previous channel is connected to the first information input of the second comparison block of the subsequent channel, and the second information input of the second comparison block of the last channel is connected to the first information input of the second comparison block of the first channel. The second input of the fourth element OR of each subsequent channel is connected to the first input of the fourth element OR of the previous channel, and the second input of the fourth element OR of the first channel is connected to the first input of the fourth element OR of the last channel.

 The first information input of the first block 16 of the comparison of each channel is connected to the control output of the reserved block of the same channel. The second information input of the first block 16 of the comparison of each previous channel is connected

0 With the first information input of the first comparison block of the first comparison block of the subsequent channel, and the second information input of the first comparison block of the last channel is connected to the first information input of the first comparison block of the first channel.

The delay unit 11 (Fig. 2) contains an input element AND 18 connected to the information V and clock inputs of the block, an input inverter 19, an output inverter 20 and memory cells, the number of which is determined by the required delay time and pulse frequency generator 12 clock pulses Each memory cell consists of the element OR 21, the element And 22 and the capacitor 23.

5 The side output is the output of the inverter 20. The first comparison unit 16 (FIG. 3) contains two elements AND 24 and 25, the outputs of which through the element 26 OR and through the chains of inverters 27 (the number of inverters is even) connected to its output are connected with the inputs of the OR element 28, the output of which is connected to the output of the block and to the first input of the element OR 29, the second input of which is the installation input of the block and the output connected to the first inputs of the AND 24, 25 elements. The second and third inputs of the AND 24 element directly, and element 25 through inverters 30 and 31 are connected with responsibly to the first (xi) and second (LGA) data inputs of the block.

The second comparison block 17 (Fig. 4) contains a three-input element AND 32, the output of which is through a chain of an even number of inverters 33 and is directly connected to the corresponding inputs of the first element 5 OR, the output of which is connected to the output of the block and to the first input of the element 35 OR whose second input is the installation input of the block and the output is connected to

the first input element And 32. The second and third inputs of the element And 32 are connected respectively to the first (x) and second (2) information inputs of the block.

The initial startup unit 1 (Fig. 5) can be made on the basis of a reed switch, the winding 36 of which is connected through a capacitor 37 to a power source, the normally closed contact 38 is connected to the first output of the unit and through a resistor 39 to a power source, a capacitor

40 through normally open contact

41 and resistor 42 is connected to a power source and to resistor 43 connected to the second output of the unit.

The first 9 and second 10 restart blocks (Fig. 6) are made according to the same schemes and contain a reed switch 44, a winding connected to the input of the block, through the contact of which the capacitor 45 is connected to the output of the block and a resistor 46 and through a resistor 47 to the power supply.

The zeroing unit 2 (Fig. 7) can be performed on two reed relays 48 and 49, the winding of the first of which is connected to the input of the unit, the winding of the second is bounded by a capacitor 50 and through the normally closed contact 48.1 of the first relay 48 is connected to a power source and normally open contacts 48.2 and 49.1 are connected in parallel and connected to the output of the unit and through a resistor 51 to the power supply.

The majority element works as follows.

When the device power is turned on, the capacitor 37 is charged in the initial start-up unit 1 (Fig. 5). At the same time, at the time of charging the capacitor 37 from its charging current, the relay 36 is triggered. As a result, at the first output of the unit 1, a positive potential from the power source through the resistor 39 appears. Parameters of capacitors 37 n 40, resistor 42 and relay 36 it is taken in such a way that the capacitor 40 has time to charge before the relay 36 is activated and the positive polarity pulse at the second output of unit 1 appears simultaneously with the signal at the first output.

The zeroing signal from the first output of block 1 through the second element OR 4 enters the zeroing inputs of the reserved blocks 6, and drives them to their initial state. At the same time on the corresponding control and information outputs of the reserved blocks 6 will be the same signals. Under this condition, as well as upon receipt of a positive pulse from the second output of unit 1, the first comparison units 16 are activated through the third element 13 OR.

The first comparison unit 16 (FIG. 3) operates as follows.

When a trigger pulse arrives at the trigger input and the same signals

five

0

0

five

0

five

five

0

five

0

On the first and second information inputs, for example, logical units, an AND 24 element is triggered and a logical unit signal appears at the output of the block. This signal, via the EV element OR 29, arrives at elements AND 24, 25 after the termination of the trigger pulse at the installation input. When the logical and zero signals arrive at the first and second information inputs, element 25 works in a similar way, for which these signals are inverted by elements 30 and 31. If the signals at the first and second information inputs differ, the logical zero signal appears at the output of the first comparison unit. which locks the elements 24, 25 and in order to turn on the comparator unit, a triggering pulse is required at the installation input. To protect against "dangerous conditions", a chain of an even number of inverters 27 is inserted in the comparison blocks, providing the necessary signal delay.

The second comparison block 17 (Fig. 3) operates as follows.

When a triggering pulse arrives at the setup input of the logical unit signals, elements AND 32, OR 34 are triggered at the first and second information inputs, and a logical unit signal appears at the output of the block. This signal, through the OR element 35, is fed to the AND element 32 after the termination of the trigger pulse at the installation input. For any other input set on the perimeter and the second information inputs on the output of the AND 32 element, a logical zero signal appears, which locks the AND 32 element through the OR 34 and 35 elements, and to turn on the second comparator unit 17, a triggering pulse is required . To protect against false triggering of the comparison unit, a chain of an even number of inverters 33 is inserted in it, providing the necessary signal delay.

In the presence of signals of a logical unit, the signals of a logical unit also appear at the output and first information inputs of the second comparison units 17 at the output of the first comparison units 16 through the fourth element 15 OR. At the same time, the second element AND 7 opens, letting the third element AND 8 and the delay block 11, since the second input of the third element 8 AND receives the signal of the logical unit from the output of element 14 NAND, the inputs of which contain the signals of logical zero.

Delay unit 11 is a shift register (Fig. 2) consisting of memory cells, the number of which is determined by the required amount of time delay. This time is selected from the condition of a full health check of the reserved

blocks 3. The block works as follows.

If there is a signal of a logical unit at the information input and the arrival of the first clock pulse at the clock input from block 11, input element 18 opens. During the pause between the first and second clock pulses, element 22 of the first cell opens, provided that the element 18 was opened before that During the second clock pulse, the elements 18 and the second cell element 22 are opened, in the pause between the second and third clock pulses the elements 22 of the first and third cells are opened, etc. The OR 21 elements and capacitors are necessary to ensure reliable operation of the And 22 elements on the leading edge of the clock pulse and to fulfill the order of their order of priority.

When element 22 of the last cell triggers, the signal of a logical unit appears at the output of its element OR 21, which is fed to the output of the block through the inverter 20. The signal of the logical zero from the output of delay block 11 is fed to the input of the second restarting unit 10, producing a short pulse for the expense of the discharge of the precharged capacitor 45 (Fig. 6). This impulse arrives at the inputs of the second comparison block 17 (Fig. 4, which are turned on and the signals of the logical unit appear at their outputs. These signals through the AND-HI element 14 are switched to the one state through the third And 8 element, the delay block 11 and open the first elements And 5, through which the first (output) element 3 OR devices receive information signals from the outputs of the reserved blocks 6.

When a short-term failure or failure of one of the blocks 6, for example, block 6-1, occurs, the signals of the logical zero appear at the outputs of the first blocks of comparison 16.1 and 16.3. A logic zero signal appears at the output of the fourth element 15 OR, and the logic zero signal also appears at the outputs of blocks 17.1 and 17.3. As a result, the first elements 5.1 and 5.3 are closed and the signals from the information outputs of blocks 6.1 and 6.3 do not pass to the device output. At the same time, the other two blocks 6.2 and 6.3 continue to function correctly, which is checked by the first comparison block 16.2, at the output whose signal is a logical unit.

Through the fourth elements 15.2 and 15.3 OR, signals of a logical unit are received at the second comparison block 17.2. As a result, the output of the second comparison block 17.2 produces a signal of a logical one, which keeps the first element 5.2 open in the open state. from the information output of block 6.2.

When logical zero signals appear at the outputs of the first comparison blocks 16.1 and 16.3, the second And 7 element is turned off, which starts the first restarting unit 9 and the zeroing unit 2. As a result of the de-energization of the relays 48 (Fig. 7) and 44 (Fig. 6), the blocks 6 are zeroed out, and the first blocks 16 of the comparison are restarted. If blocks 16.1 and 16.3 turned off as a result of a failure, after the completion of zeroing pulses, their normal operation should be restored and restarted, and the signals of the logical unit will be outputted to the outputs. In this case, the second element 7 will work, at its output the signal of a logical unit will follow, followed by the third element 8, since the signal of the logical unit from the output of the element AND-NOT 14 will come to its second input. As a result, block 11 will start working delays. The delay time of block 11 is determined by the time for complete control of the correct functioning of redundant blocks 6. If during the delay time these blocks function correctly, then the second comparison blocks 17 are started with the help of the second restarting block 10, the first elements 5.1 and 5.3 open, and normal operation device is restored.

In the event of a failure in one of the blocks 6, for example, 6.1 after their zeroing, the restoration of the normal operation of the device does not occur. The first blocks of comparison 16.1 and 16.3 are turned off, the logical zero level is maintained at the output of the second element 7 I, and the delay block 11 is not started. This eliminates the connection to the device output of the signals of the failed redundant block 6.

In the event of a failure or failure in one of the first comparison blocks 16, a logical zero signal appears at its output, as a result, the second And 7 element turns off and the device restarts and restores (in the event of a failure) as described above.

In the event of a failure or failure in one of the second comparison blocks 17, a logical zero signal appears at its output and the corresponding first element AND 5 turns off. At the same time, the signal of the logical unit appears at the output of the IS 14 element, and the third element 8 is triggered, a delay unit 11, after which the corresponding unit 17 is started through the second restarting unit 10. When a failure occurs in one of the redundant units 6 of the device during the delay or after it ends, if there is a device failure, completely off yuchayets.

The signals at the outputs of the first 16 and second 17 comparison blocks are used to determine the state of the device as follows.

If at the outputs of all listed blocks there are sigals of a logical unit, then the device is intact. If at the outputs of the two first stage comparison units and the corresponding two second stage comparison units a logical zero signal is present, then a failure occurred in one of the redundant units 6, and when the 16.1, 16.3, 17.1, 17.3 units were turned off, the failure occurred in block 6.1. When turning off the sides 16.1, 16.2, 17.1 and 17.2, a failure occurred in block 6.2; and when turning off the blocks 16.1 and 16.3, 17.2 and 17.3 - in block 6.3.

If the logic zero signals appear only at the output of one of the blocks 16, then the failure occurred in this block 16. If the signal of the logical zero occurred only at the output of one of the blocks 17, then the failure occurred in this block. Thus, the proposed device does not require additional elements for diagnosing failures.

For each of blocks 6, the information output is the output of the block, and the control output is the control point in the redundant block scheme, which includes the information output.

In the absence of such control points, the information output of the corresponding redundant unit 6 should be connected to the inputs of the comparison block 16.

Claims (1)

Invention Formula The majority logical element containing the initial start-up unit, the zeroing unit, the first and second OR elements and in each channel the first AND element, the first input of which is connected to the information output of the reserved block of the corresponding channel, and the output connected to the corresponding input of the first OR element, the output of which is connected to the output of the device, the output of the second element OR is connected to the inputs of the initial installation of redundant blocks of all channels, the first and second inputs of the second element OR are connected respectively About the output of the zeroing unit and the first output of the initial start-up unit, characterized in that, in order to increase the reliability of the operation, the second and third AND elements are introduced into it; first and second restart blocks, delay block, generator so 0 five five 0 about 5 of the first pulses, the third OR element, the NAND element and the fourth OR element, the first and second comparison blocks, the input input of the first comparison block of each channel are connected to the output of the third OR element, the first and second inputs of which are connected to the second output, respectively. of the initial start-up block and the output of the first restart block, the input of which is connected to the input of the zeroing block, the first input of the third And element, and the output of the second And element, the inputs of which are connected to the outputs of the first blocks comparison and the first input of the fourth element OR of the corresponding channel, the output of the fourth element OR is connected to the first information input of the second comparison unit of the same channel, the setup input of which is connected to the output of the second restarting unit, the input of which is connected to the output of the delay unit, clock and information inputs which is connected respectively to the output of the clock pulse generator and the output of the third elem..1y And, the second input of which is connected to the output of the element AND-NOT, the inputs of which are connected to you the second input unit and the second channel, the second information input of each second comparison module of the previous channel is connected to the first information input of the second comparison module of the subsequent channel, and the second information input of the second comparison module of the last channel is connected to the first information input of the second comparison unit the first channel, the second input of the fourth element OR of each subsequent channel is connected to the first input of the fourth element OR of the previous channel and the second input of the fourth element OR of the first channel is connected to the first input of the fourth element OR of the last channel, the first information input of the first comparison block of each channel is connected to the control output of the reserved block of the same channel, the second information input of the first comparison block of each previous channel is connected to the first the information input of the first comparison block of the subsequent channel, and the second information input of the first comparison block of the last channel is connected to the first information input the house of the first block comparing the first channel. 2nd Sbixod Phage.5 B) (0d 0 44 Ti Output 6 f Output