SU1248057A1 - Buffer device - Google Patents

Abstract

The invention relates to a pulse technique and can be used as a device to match the injection logic elements. The aim of the invention is to increase the speed, efficiency, load capacity and decrease the input current. To achieve this goal, new functional inter-element communications are used in the device, and the first transistor is filled with an emitter area larger than that of the second transistor. The drawing shows transistors 1 and 2 of p-and-p-type, transistors 3 and 4 of hph-type, current generator 5, power supply bus 6, device input 7, device outputs 8.1-8.A /, injection element 9. The device can reduce the level of currents of current generators of controlled injection elements and, without sacrificing speed, can be reduced by the consumption of MOFHHTTb. 1 cs.f.le, 1 ill. i (Luo 42 00 Oh cl 4j

Description

The invention relates to a pulse technique, namely to devices for matching with injection logic elements.

The aim of the invention is to improve the speed, efficiency, load capacity and decrease the input current.

The drawing shows a schematic diagram of a buffer device with an injection unit 1 m connected to one of its outputs.

The buffer device contains the first and second transistors and 2, pnp-type, third and fourth transistors 3 and 4 pnp-type, current generator 5 embedded in between the power line 6 and the emitters of transistors 1 and 2, the base of transistor 2 and the emitter of transistor 4 are connected to a common bus, the collector of transistor 2 is connected to transistor 4, and 3. The collector of transistor 3 is connected to the base of transistor 1, the emitter of transistor 3 is connected to device 7, and each collector of transistor I is connected with the corresponding collector of transistor 4 and the corresponding m output 8, 1-8. l / device output 8.1 is connected to the input of the injection element 9.

The buffer device works in the following way, o1a; and 5.

At a positive level of the signal input to the device 7, the transistors 1 and 3 are closed, and the transistors 2 and 4 are open (-1ty and at the outputs 8 of the device connected to the injection elements 9, a voltage is generated; The signal level at the input 7 of the device reaches the common bus potential of transistor 3. When the level of the signal is lowered further, transistor 3 opens and transistor 4 closes. At the same time, the currents of current generators of injection elements 9 at outputs 8 .1 -8. F devices are configured on log, 1. At this time, the transistor 1 is opened and the current generator 5 current is redistributed between transistors 1 and 2, and the current of the transistor's current components begins to additionally go out at the device outputs 8, I-8.N. device into the load, is determined by the following EIM:

and-

() (1 lm

()

Where

iff - current generator 5 current; gain factor

p-and-transistor; p is the gain of the pn transistor.

The switching time is determined by the turn-on time of transistor 4. Transistor 3 can saturate at a negative input signal level close to the potential of the common bus. This causes the additional current of the input signal to cause an additional current to the base of transistor 4, due to the dissipation of the excess charge in the base of the transistor 3, which leads to a decrease in the turn-on time of the transistor 4, i.e. the switching time of the device from the state of log.1 to the log.O state is equal to the turn-on time of transistor 4.

In the state of the log. the current supplied by the expression (1) enters the load. From this expression determines the efficiency of the device in the state log.1

(()

(2)

The efficiency coefficient of the device can be further increased if the emitter area of transistor 1 is made larger than the emitter area of transistor 2.

In the proposed device, a part of the current of the constant current generator flows into the load, which leads to a decrease in the flowing input current of a low level.

The proposed device has a high load capacity, since it is multi-output.

The buffer device in the state of log.1 imposes a current into the load, which allows in a number of cases to reduce the level of currents of current generators of controlled injection elements, and even to make it equal to zero and without sacrificing speed, to reduce the power consumed by the circuit.

Claims (2)

1. The buffer device containing the first and second transistors 312480574 р-и-р-type, the emitters of which are connected — the base of which is connected to the collector with the current source, the third element of the third transistor, the base the fourth transistors and-p-and-type, the third transistor is connected to the base of the second and the fourth emitter is the collector of the second transistor, and transistors are connected to the common 5 additional collectors of the first bus, the collector of the second transistor transistor connected to the corresponding connection to the base of the fourth trans-F1 F and additional collectors a resistor whose collector is a fourth transistor and is associated with an output, an emitter with third-party additional outputs. the transistor is connected to the input of the device-10 device, which is characterized by that in order to increase the speed 2. The device according to claim 1, about t l and STI, efficiency and load capacity is the fact that the first and reducing the input current, the collector transistor is made with the area of the fourth-fourth transistor connected to 15ter larger than that of the second transcollector of the first transistor, the resistor.