SU1247855A1 - Information input device - Google Patents

Abstract

The invention relates to the field of automation and measuring information technology and is intended for switching and converting analog signals. The purpose of the invention is to improve the accuracy of the results of measurement (L yu 4 CX)

Description

rhenium. The essence of the invention is that in the device containing elements I-6, element 7, delay elements 8-10, serially connected clock pulse generator P, counter 12 and decoder I3, which controls the switchboard of signals from sensors, the output of which the amplifier 15 and the direct or inverting circuit selected by means of a comparator and a polarity trigger 18 are connected to the input of an analog digital conversion circuit with an intermediate voltage-time conversion; two multi-bit circuits are introduced

The invention relates to automation, measuring information technology and is intended for switching and converting analog signals with a wide dynamic range into a digital equivalent, and can be used as an external device for measuring information systems and control computing complexes.

The purpose of the invention is to improve the accuracy of measurement results,

The drawing shows a functional diagram of the proposed device for entering information.

The device contains six elements AND 1-6, the element NOT 7, three delay elements 8-11, the first pulse generator 11, the counter 12, the decipher, the torus 13, the multiplexer 14, the amplifier 15 the first 16 and the second 17 keys, the first trigger 18 inverting repeater 19, comparator 20, block of elements OR 21, first element OR 22, reversible counter 23, two registers 24 and 25, master oscillator 26, voltage converter 27 to time interval, third key 28, quarter delay element 29, the seventh element And 30, the second trigger 31, is the second element ШШ 32.

The information input device operates as follows.

According to the signals from the clock pulse generator 11, the counter 12 sets the register 24-25 connected to the outputs and inputs of the reversing counter 23, the counting control inputs of which are connected to the outputs of the polarity trigger 18. The first and second outputs of the decoder block the gate sampling and unlock the registers 24 and 25, in which the current offset value is recorded for signals of positive and negative polarity. To measure the signal offsets from the first and second outputs of the decoder, a switch 28 is closed which connects the output of the switch to the zero-potential bus, 1 slug.

hence the increasing code by. the decoder 13, on the outputs of which successively appear the signals controlling the switching of the channels of the multiplexer 4 or the key 28 for connecting the zero signal to the input of the measuring path.

The first two channels are diverted to measure displacements in the measuring

tract when measuring positive and negative signals. The input of the measuring path is then zero, the signal through the third key 28, closed as it passes

measurements on the first and second channels, t, e, at the beginning of the measurement cycle. For this, the control input of the third key 28 is given a control signal From the output of the second element OR 32,

the inputs of which are connected to the first and second outputs of the decoder 13. From the same outputs of the decoder 13, the signals arrive at the installation inputs of the first trigger 18. When operating on

The first channel trigger 18 is reset and the measured signal from the amplifier unit 15 is fed to the input of the voltage converter 27 at a time interval through a switch 16 (positive input signal). The signal from the clock generator 11 also triggers the analog-to-digital conversion procedure: resetting the reversing counter 23, rewriting through the time determined by the delay circuit 9, to

the trigger 18 for controlling the polarity of the current value of the output signal from the polarity comparator 20 applied to the input of the trigger 18, setting through the delay element 29 to the unit state of the second trigger 31 determining the time interval of the voltage conversion - time for filling the reversible counter 23 by counting pulses of the reference frequency from the generator 26 through the element AND 4 and the element OR 22. Resetting the trigger 31 is performed from the voltage conversion unit 27 into a time interval, for example, by the charging circuit the capacitor, followed by discharge of its reference current and the determination of the moment of zero crossing of the charge of this capacitor.

As a result of the analog-to-digital conversion cycle on the reversible counter 23, an additional CID of the numerical equivalent of the input signal is formed, since the counting direction will be determined by the state of the polarity 18 trigger.

When polling the first and second channels, the offsets in the measurement cycle are measured. For this, the signals from the first and second outputs of the decoder. 13 are combined on the OR element 32 and are fed to the control input of the third key 28, the closure of which leads to the connection to the measuring path of the zero signal from the zero potential bus. In this case, the polarity trigger 18 is set by the setup inputs to the zero (first channel of the decoder 13) or to the single (second channel of the decryptor 13) state for the entire analog cycle time; digital conversion. According to the first

channel offset for branch

positive input signals (amplifier 15, first key 16), according to the second - dp negative (amplifier 15, second key 17, inverting repeater 19). Let us denote the results of measuring these displacements, respectively, N and N. Registers 24 and 25, when measuring, rhenium displacements are locked, since the pert element I 3 through the element HE 7, the elements I 1 and 2 are open, with the result that after an analog-to-digital conversion cycle, the results of measurements of N and Nj, respectively, rewrite 10 t5 20

. 25

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Sanaas from the output of counter 23 to registers 24 (for polkitelny input signals) and 25 (for negative input signals). The rewriting is performed according to the signal from the clock pulse generator 11, which is delayed by the delay elements 9 and 8 for the time of the A / D conversion cycle. Element I 37, which generates synchronization signals 11; and an external recorder of measurement results (arriving at the device’s general output) for the time of measurement of displacements, is blocked by a signal from the HE element 7.

The remaining input channels (beginning with the third one) are intended for measuring signals from working sensors. The trigger 18 records in this case the state of the comparator 20, since the setup inputs of the trigger 18 no longer affect its state. Strobe formation circuits for registers 24 and 25 (coincidence circuits 3, 5, 6) are unblocked and depending on the polarity of the input signal, counter 23 records the code from register 24 (for negative input signals) or register 25 (for positive input signals) .

one

The census is done after

the initial reset of the counter 23 and the installation of the trigger 18 with a delay determined by the delay element 9 for the transient time in the multiplexer 14 before the addition of the unit to the counting input of the counter 23 through the delay element 10 (the delay time is determined by the code 24 and 25 at the counter 23). The rewrite of N, (from register 24) and N (from register 25) codes in inverse form and adding them to the unit at the counting input allows to obtain at counter 23 the value (-N) or (-N) presented in the additional code (for subsequent subtraction operations). Further, with some delay on the delay element 29, the signal of the beginning of the analog-time conversion cycle is produced, which sets the trigger 31 to the one state, after which the counter 23 input receives pulses from the generator 26 through the AND 4 element and the OR 22 element. either in the summation mode (for positive input signals), or in the subtraction mode (1dl negative input signals).

Let the counting input go And pulses. They are associated with input signal and dependency.

N "and + N

where k

f 5

conversion ratio of the measuring path; N - offset in measuring

path for the corresponding PN: er About the state of the polarity trigger 20 (NB N. for

w,

, Np. ,, Wj for p 1).

Since before the beginning of the va-log-digital conversion cycle, the counter (23) is assigned the code (-Cp)

N - NJ, K

(2)

proportional to the magnitude of the non-input signal, taking into account the sign of the latter and presented in an additional code, which is commonly used in computing.

This value is set on the common output of the device along with the synchronization signal:, r of the recorder, post: a; l {s with cxei 2 i matches 30 after the conversion conversion is finished, the time is set by the delay circuit. The following is: - chi; s ,,: mcccc, measuring path of the driylosh.a :: quantity, which at: - may have both positive and negative values. This is automatically taken into account by the proposed structure: y: yo device. The only condition for the correct functioning of the device is the preservation of the significant input signal during its selection by the analog-digital conversion circuit (from the moment of rewriting the polarity on the trigger 18 to the end of the charge of the capacitor in the voltage converter 27 in the time interval determined by the control signal The input of the converter is 27 s, and the delay skeleton 29 is displayed.

The proposed device for entering information in comparison with the known one has a greater accuracy and a more convenient form for presenting the result by measuring the nprf measurements of maintaining the device speed. This can be confirmed by the fact that in a known device the presence of an offset in the measuring path and its drift, which is

five

0

five

0

five

five

0

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The latter are usually units of millivolts and tens of microvolts per degree, respectively. If the scale of the measuring device is designed, for example, at 10 mV with a sensitivity of 10 µV, this leads to the following: The accuracy of the proposed device in comparison with the known is improved by 5-1Q times. The form of presentation of the final results in the additional code that takes into account the sign of the input signal allows a 10-20% decrease in the total time of the last; - data processing on a computer.

Claims (1)

Invention Formula The device for B.. keys, inverting repeater, comparator, first trigger, output of the first generator impulse-. ow is connected to the input of the counter and the input of the second element of idle load s, the output of which is connected to nepso; - y the input of the third element I, s:; the inverse outputs of which are connected to the control inputs of the first and second keys, respectively, and to the second inputs of the fifth and sixth elements AND, the outputs of the counter are connected to the inputs of the decoder, the first and second terminals of which are connected to the third and second inputs of the first trigger, respectively, and to the first inputs the first and second And elements, the other outputs of the Depthfrarator are connected to the address inputs of the multiplexer, whose information inputs are the device inputs, the output of the multiplexer is connected via an amplifier to the I / O Formation inputs of the first and second keys and to the input of the comparator, the output of which is connected to the first - input of the first trigger, the output of the second key is connected to the input of the inverting repeater, the output of the element is NOT connected to the second input of the third element delay and to the first inputs of the fifth and sixth elements And, the output of the first delay element is connected to the second The inputs of the first and second elements AND are characterized in that, in order to improve the accuracy of the measurement results, the block of the elements OR, the first and second elements -OR, the reversible counter, the first and second registers, the second pulse generator, the voltage converter in the time interval , the third key, the fourth delay element, the seventh element And, the second trigger, the outputs of the first and second elements And are connected to the write inputs of the first and second registers, the outputs of the fifth and sixth elements And are connected to the inputs of the link first and second registers are connected to the inputs of an OR block whose outputs are connected to the preset inputs of a reversible counter, whose outputs are information outputs of the device, the corresponding information inputs of the first and second registers are combined and connected to the outputs of the reversible counter, the first input of the seventh element AND is connected. To the output of the first delay element, and the second input is connected to the output of the element NO, the output of the seventh element AND is the sy by the synchronization output of the device, the input of the fourth delay element Editor I. Segl nick Compiled by V. Bazovkin Tehred M. Khodanich Proofreader L. Pilipenko Order 4126/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 47853. eight connected to the output of the second delay element, and the output connected to the first input of the second trigger and to the control input of the converter, for the time interval whose output is connected to the second input of the second trigger, whose output is connected to the first input of the fourth element And, the output of which is connected to 10 the second input of the first OR element, the first input of which is connected to the output of the third delay element, and the output is connected to the counting input of the reversible counter, the reset input of which is connected to the output of the first the pulse generator, the first and second control inputs of the reversible counter are connected to the direct and inverse outputs of the first trigger, respectively, the output of the second pulse generator is connected to the second input of the fourth element And, the outputs of the first key and the inverting repeater are connected to the second analog input 25 of the voltage converter in the time interval, the inputs of the second element OR are connected to the first and second outputs of the decoder, and the output is connected to the input of the element NOT and to the control input of the third the key whose output is connected. On the zero potential bus, the information input of the third key is connected to the multiplexer output.