SU1243032A1 - Storage with self-check - Google Patents

Abstract

The invention relates to memory devices and can be used in avomatics and computer systems. The aim of the invention is to increase the reliability and speed of the device. The device contains a drive, first, second and third registers, an error detection and correction unit, first to fifth switches, a comparison unit, a control bit correction unit, a coding unit, first, second and third triggers. The device allows you to continuously monitor the operation of the coding, error detection and correction blocks by simultaneously submitting information read from the accumulator to their inputs and comparing the generated codes in the comparison block, reduce the recording time in the data storage with different formats by preliminary reading the information and replacing part of it to a new one with a subsequent entry with the newly formed check bits. 5 il. F (L tc 4 OO O 00 iNd

Description

The invention relates to memory devices and can be used in automation and computer systems.

The purpose of the invention is to increase the reliability and speed of the device.

FIG. 1 is a schematic diagram of a self-monitoring memory device; FIG. 2 is a diagram of the third switch j in FIG. 3 is a diagram of the fourth switch; in fig. 4 is a diagram of a check bit correction block; FIG. 5 is a schematic of an error detection and correction unit.

The memory device (Fig. 1) contains a drive 1, a first register 2, an error detection and correction unit 3, a first switch 4, a second switch 5, a fourth switch 6, a five switch 7, a comparison block 8, a check bit correction unit 9, coding unit 10, third switch 11, second trigger 12, first trigger 13, second register 14, third register 15, third trigger 16, input 17 Word address, inputs 18 Micro-command, input 19 Output, inputs 20 OD data, inputs 21 Result of CPU , input 22 Key input 23 Control, outputs 24 Control, output 25 Equipment failure No, input 26 Double word recording, inputs 27 CPU data, inputs 28 Masks input 29 Parity, input 30 Mode, input 31 Blocking, inputs 32 Microcommand setting, inputs 33 Synchronization, output 34 Double error, output 35 Input data error, line l zi 36-47 between blocks.

The third switch (Fig. 2) contains the first element NOT 48, the second element NOT 49, the first group of elements AND-OR 50, the second group of elements AND-OR 51, the third group of elements AND-OR 52, the fourth group of elements VOB I-III 53, register 54.

The fourth switch (Fig. 3) contains the first AND-NOT element 55, the second AND-NE element 56, the first inverter 57, the second inverter 58, the first group of AND-59 elements, the second group of AND-OR elements 60, the register 61 the third group elements AND-OR 62, the fourth group of elements AND-OR 63, the third inverter 64, the first adder 65 modulo 2, the second adder 66 modulo 2, the element AND-OR 67.

The control bits of the control bits (Fig. 4) contains the first inverter 68, the second inverter 69, the first element AND 70, the third inverter 71, the second element NOT 72, the first group of elements AND 73, the second group of elements AND 74, the first group of adders 75 modulo 2, the second group of adders 76 modulo 2, register 77.

The onibok detection and correction unit (Fig. 5) contains a comparison node 78, a register 79, a decoder 80, an adder 81 modulo 2, a node 82

forming the control bits of the Hamming code, adder 83 modulo 2.

The locking device with self-monitoring can operate in two diagnostic modes. The first diagnostic mode allows you to check the status of individual memory bits, both informational and control, the second - to artificially create a single error in a given bit.

.informational words. Taken together, both modes allow you to fully test the operation of the storage device.

Fixing device in the first

diagnostic mode works as follows.

At input 30, the mode is set to trigger Parity mode 12. This trigger blocks reception in register 79

block 3 detection and correction of errors, as well as blocking block 9 correction check bits. It also prohibits the correction of information read from accumulator 1. In this mode, the data written to the accumulator comes from the processor through the inputs 27 AH data. The size of this data is 4 bytes. They are written to drive 1 along with their parity bits, which are fed in input 29 Parity to the input of switch 11. A double word is written to the drive in two write cycles. Together with a double word instead of code bits

Hamu nga are recorded parity bits. Thus, tests of the type of running zero running unit, as well as other more complex tests, can be used to check the check bits. When reading from the accumulator, 1 written double word is sent through the switches 5 and 7 to the processor.

bits in the form in which they were recorded in drive 1. Comparing them with the standards allows us to objectively judge the state of any bit located at any address of the drive 1 double word.

This mode also makes it possible to check the correctness of the formation of the Hamming code by the encoding unit 10. In this case, the verification is carried out as follows. First, in standard mode, accumulate 1 records reference double words, for each of which block 10 forms its own

check bits of the Hamming code. After the switch 11 skips the control

25

thirty

35

THIS is set by the trigger of the Parity mode 12 and double words are read from accumulator 1 with the control bits of the Hamming code that were formed by the unit J.Srav-- ,. their field with the standards, it is possible to judge the correctness of the operation of block 10 (in this case it is assumed that drive 1 has already been tested).

In the second diagnostic mode, the self-monitoring memory device operates as follows.

At a fixed address, a specific double word is written to the drive. The encoding unit 10 generates a certain Hamming code for it. Thereafter, at the input 31, the blocking is set to 1 blocking trigger 13. This trigger blocks reception in the register 14. If we now write to the drive 1 a new word that differs from the old one by one bit, then instead of the control bits of the Hamming code generated by coding unit 10, the control bits of the Hamming code remaining in register 14 from the last entry. Thus, a single error is created in this double word. If we now read this double word from accumulator 1, then error detection and correction block 3 will form syndromes indicating the number of the failed bit and the number of the byte in which this bit is located. These syndromes are output to the processor via switch 7. Corrected data is output via switch 5 to the processor. Comparing them with the standard, you can judge the correct operation of the storage device. The correct formation of the Hamming code in block 3 is accomplished by comparing it with the Ham40 code

45

50

55

bits of the Hamming code, formed by coding block 10. In the diagnostic mode, the switch 11 transmits information from Parity input 29 and from register 2 outputs.

The fourth switch 6 (Fig. 3) is designed to form a double word that needs to be written to drive 1. The information that needs to be written to drive 1 is received at inputs 20, 27 and 29. At inputs 20, the OD data are supplied by a double word (eight bytes). A signal at input 26 Writing a double word determines the transmission of this double word to the input of accumulator 1. If there is no resolution at input 26, switch 6 transmits information from input 27 Data of the CPU with test bits from input 29 Parity. 4 inputs are received on inputs 27. Which word in the written double word will be new, and which will remain unchanged, is indicated by the input state of 17 Word Addresses. If the state of this input is 1, then 4-7 bytes of the double word read from drive 1 will be replaced. Otherwise, bytes 0-3 change.

Within the limits of the word recorded in Drive 1, some bytes are allowed not to change. The positions of these bytes in the word are determined by the Mask inputs. The bytes of the written double word that remain unchanged are entered into the switch 6 of block 3, which they previously read from the accumulator 1 as part of the double word, and in case of an error it is corrected. The switch 6 controls the parity of the data entering the storage device at the inputs 20 OD data or 27 Ladies

unit, by block 10, (this assumes that block 10 has already been verified).

Thus, the storage device is checked in the following sequence: check of accumulator 1, check of decoding unit 10, check of single error correction mode.

The third switch 11 (FIG. 2) is intended for switching the control bits written to drive 1 together with the corresponding double word. In working mode

five

0

,

0

five

0

five

bits of the Hamming code, formed by coding block 10. In diagnostic mode, the switch 11 passes information from the input 29 Parity and from the outputs of the register 2.

The fourth switch 6 (Fig. 3) is designed to form a double word that needs to be written to drive 1. The information that needs to be written to drive 1 is received at inputs 20, 27 and 29. At inputs 20 of the OD data, a double word (eight, bytes). A signal at input 26 Writing a double word determines the transmission of this double word to the input of accumulator 1. If there is no resolution at input 26, switch 6 transmits information from input 27 Data of the CPU with test bits from input 29 Parity. The inputs 27 receive 4 bytes. Which word in the written double word will be new, and which will remain unchanged, is indicated by the input state of 17 Word Addresses. If the state of this input is 1, then bytes 4-7 of the double word read from drive 1 are replaced. Otherwise, bytes 0-3 change.

Within the limits of the word being written to the drive 1, some bytes are allowed not to change. The positions of these bytes in the word are determined by the Mask inputs. The bytes of the written double word, which remain unchanged, are sent to switch 6 from block 3, which they previously read from drive 1 as part of the double word, and in case of error it is corrected. The switch 6 controls the parity of the data entering the storage device at the inputs 20 OD data or 27 Ladies

CPUs and 29 Parity. In the event of a fault, a signal is output to output. 35 Input data error.

A parity trigger 12 determines a diagnostic mode in which the state of all bits of a double word read from accumulator 1 is checked.

The check bit correction block 9 makes it possible to shorten the cycle time of writing to the drive 1 word or several bytes of this word. In this case, the follower: The new action looks as follows:

double word memory sampling,

replacing in this double word four bytes or less (bytes 0/3 or 4/6) I

Writing a newly formed word After reading from the double word accumulator 1, it is analyzed for an error and corrected for this error. This BpeivM takes approximately 25 of the entire write cycle. To shorten the write cycle, simultaneously with the analysis and correction, the read double word enters the switch 6, where a new double word is formed, and for it the coding block 10 generates a Hamming code, which is written to register 77. By this time, in case of an error at output 37 of block 3 detection and correction. non-zero syndrome is formed of errors. If the error is detected in bytes to be replaced, the groups of elements And 73 and 74 are blocked, the output of the Hamming code from the register 77 is output to the output 42 of the block 9 for correcting the control bits. If the error is detected in the byte that is not to be replaced, then the syndromes pass through the groups of elements And 73 and 74 to the inputs of adders 75 and 76 modulo 2 and invert the bits of the Hamm code nga in register 77.

The error detection and correction unit 3 (Fig. 5) is designed to correct single errors in a double word read from accumulator 1 to the first register 2. The information bits are input to the node 82 of the formation of the control bits of the Hamming code. The generated Hamming code, as well as parity bits from the output of the node 82, are fed to the input of the comparison node 64 and the adder 83 modulo 2. To another input of the node 79 enters 0

five

0

:five

0

five

0

five

The control bits of the Hamming code from the first register 2 are received. The results of the comparison (syndrome) are entered into register 79, from the output of which the syndrome enters the decoder 80. If the syndrome is not zero, the output of the decoder 80 indicates the number of the failed bit. In this case, cymatop 81 modulo 2 inverts this bit, and the sum of torus 83 modulo G inverts the parity of the byte containing the faulty bit. In the case of a double error, the decoder 80 generates the corresponding signal. The output to the processor from block 3 is transmitted on outputs 44.

Claims (1)

Invention Formula A self-monitoring memory device containing a drive, information inputs of the first group of which are connected to the inputs of the coding unit, information inputs of the second group are connected to the outputs of the second register, and outputs are connected to the information inputs of the first register, the outputs of the first and second groups of which are connected to the inputs of the detection unit group and error correction, the outputs of the first group of which are connected to the inputs of the first group of the first and second switch, and the output is the first control output device The third switch, the inputs of the first and second groups of which are connected respectively to the outputs of the coding block and to the outputs of the second group of the first register, the first input of the third switch is connected to the input of the first switch and is the address input of the device, and the second input is the first control input the devices, the outputs of the first switch are connected to the inputs of the third register, whose outputs are the information outputs of the first group of the device, the inputs of the second and third groups of the second switch are corresponding etstvenno information input and first and second groups of devices, the inputs of the second group per.vogo switch and second switch outputs are respectively informa-. The third group information inputs and the second device group information outputs, the first and second inputs of the second switch, and the setup input of the first flip-flop are the first, second, and third, respectively. 7 the control inputs of the device, the synchronous inputs of the first, second and third registers, the first trigger, the third switch, the error detection and correction unit, the accumulator are the synchronization inputs of the first group of the device, the output of the first trigger is connected to the control input of the second register, characterized in that in order to increase the reliability and speed of the device, the fourth and fifth switches, a comparison unit, a control bit correction block, second and third triggers, and the inputs of the first group The first switch is connected to the information inputs of the first group of devices, the inputs of the second group are information inputs of the fourth group of the device, the inputs of the third group are connected to the inputs of the second group of the correction unit, the check bits, the first and second inputs of the fourth switch are connected respectively to the second output of the detection unit and error correction and to the first control input of the device, the third input is connected to B1; one input of the block of correction of check bits and the address input of the device, the fourth input is connected to the third input of the control bit correction block and is the fifth control input of the device, the group outputs of the fourth switch are connected to the inputs of the coding unit, and the output of the fourth switch if 243032 Torah iO 15 20 25 thirty 35 YABL is controlled by the device control output, the inputs of the first group of the control bits correction block are connected to the outputs of the second group of the error detection and correction unit and to the inputs of the first group of the fifth switch, the first input is connected to the third output of the error detection and correction unit, the fourth input is connected to one inputs of the error detection and correction unit of the fifth switch, to the third input of the third switch and to one output of the second trigger, the other output of which is connected to another input of the fifth switch, and the setup input is the sixth control input of the device, the inputs of the first group of the comparison unit are connected to the outputs of the coding unit, the inputs of the second group are connected to the outputs of the third group of the error detection and correction unit, and the output is connected to the setup input of the trigger. which is the third control output of the device, the outputs of the check bits correction block are connected to the information inputs of the second register, and the inputs of the third group are connected to the outputs of the third switch, the outputs of the fifth the switch are information outputs of the third group of the device, the synchronous inputs of the second and third triggers of the correction block. The control bits of the current type of switch are the sync inputs of the second group of the device. Phage. Z FIG. H 2B “2 FIG. Editor V. Petrash Order 3711/52 Circulation 543Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Compiled by O. Isaev Tehred M. Morgental Proofreader G. Reshetnik